Embedded system vs.

PC based system
• An embedded product uses a • A PC based system can be used
microprocessor or for any number of applications
microcontroller to do one task such that word processor, print-
only. server, video game player,
network server; internet
• A printer is an example of terminal etc.
embedded system since the
processor inside it performs
one task only; namely getting
the data and printing it.

• Other examples:
stereo equipments, washing
machine, VCRs, micro-wave
oven, photocopiers, computer
peripherals (IBM PC Key board),
mobiles etc
 Micro-Processor vs. Micro-Controller
Hardware architecture Hardware architecture
• micro-processor is a single- • a micro-controller contains in a
chip CPU, requires external single IC, a CPU and much of
ROM,RAM and other circuitry the remaining circuitry of a
complete microcomputer
system, like RAM, ROM, a serial
Applications
interface, a parallel interface,
• Microprocessors are most timers, interrupts circuitry
commonly used as the CPU in
Applications
microcomputer system (PC) in
• In a microcontroller based
order to process large
embedded system, there is only
information like word
one application software that is
processor, print-server, video
typically burned in to ROM.
game player, network server;
internet terminal etc.
 Micro-Processor vs. Micro-Controller
Instruction set features Instruction set features
• • Micro-controllers on the other
Microprocessors instruction set
are “processing intensive”, hand, have instruction sets
implying they have powerful catering to the control of inputs
addressing modes with and outputs. The interface too
instructions catering to many inputs and outputs uses
operations on large volume of a single bit.
data. Their instructions operate • For example, a motor may be
on byte, words, double words, turn on and off by a solenoid
array of data, address pointers energized by a single-bit
and offsets etc output port.
 Short birth history
8051, which was originated by Intel, several
companies also currently produce the 8051 micro-
controller. These companies include: Intel, Atmel,
Philips / Signetics, AMD, Siemens, Matra, and Dallas
semiconductor.
• In 1971 first 8080 μ-Processor introduce by INTEL
• In 1976 first 8048 μ-Controller introduce by INTEL
• In 1980 8051 μ-Controller introduce by INTEL
 MCS-51 Family Overview
The generic MCS-51 IC is the 8051, the first device in
the family. Its features are summarized below.
• 4K bytes ROM (factory masked programmed)
• 128 bytes RAM
• Four 8-bit I/O (Input/Output) ports
• Two 16-bit Timers
• Serial interface
• 64K external code memory space
• 64K external data memory space
• Boolean processor (operates on single bits)
• 210 bit-addressable locations
• 4 μ-sec multiply/divide
Comparison of MCS-51 ICs
Port 0
• Port 0 is a dual-purpose port of the 8051 IC. It can be used
as a general purpose I/O port, as well as this port becomes
a multiplexed address and data bus when interfacing
external memory with the 8051 IC.
Port 1
• Port 1 is a dedicated I/O port of the 8051 IC. No alternate
function is available for 8051 device, but in case of 8052 /
89C52 IC’s, P1.0 and P1.1 either as I/O lines or as external
inputs to the third timer.
Port 2
• Port 2 is a dual-purpose port of the 8051 IC. It can be used as a general
purpose I/O port, as well as this port becomes a high byte of address
bus and when interfacing external memory with the 8051 IC.
 BIT Name Alternate
Function
P3.0 RXD Receive data for
serial port

P3.1 TXD Transmit data for

serial port
Port 3
• Port 3 is a dual- P3.2 INT0 External
purpose port of the interrupt 0
8051 IC. It can be used P3.3 INT1 External
as a general purpose interrupt 1
I/O port, as well as P3.4 T0 Timer/ Counter 0
alternate functions of external input
each bit is as follows.
P3.5 T1 Timer/ Counter 1
external input

P3.6 WR External data

memory write
strobe
P3.7 RD External data
memory read
strobe
 Reset Operation
• The Reset input pin # 9 is the master reset for the 8051 device,
when this signal brought high for at least two machine cycles and
then returning it low, the 8051 device become reset. Reset may be
manually activated using a switch, or may be activated upon power-
up an RC network.

VCC
VCC

C2
R1 C1
SW1

RESET(Pin#9) RESET(Pin#9)

R2 R4
The states of all the 8051 registers after a system reset is as summarized
in below table

Registers Contents
Program counter 0000H
Accumulator ( ACC ) 00H
B register 00H
PSW 00H
SP (Stack Pointer) 00H
DPTR 0000H
PORT(0…..3) FFH
IP (8031/8051) XXX00000B
IP (8032/8052) XX000000B
IE (8031/8051) 0XX00000B
IE (8032/8052) 0X000000B
Timer register 00H
SCON (Serial control register) 00H
SBUF (serial buffer register) 00H
PCON (Power control register) 0XXX000B
 External Access (EA)

• The EA input signal on pin 31 is generally tied high (+5V) or low

(GND). If high, the 8051/ 8052 execute programs from internal
ROM. If low, internal memory disable and programs execute
from external memory. Memory could be RAM or ROM.

Power Connections
• The 8051 operates from single +5 Volt supply. The VCC
connection is on pin 40, and the VSS or GND on 20.

ALE (Address Latch Enable)

• An o/p pin and is active high
• This pin is used for de multiplexing data and address from
Port0. this outputs a signal that is 1/6th of crystal oscillator
 On-Chip Oscillator Inputs
On-Chip oscillator of The 8051 IC is driven by a crystal connected to
pins 18 & 19. Also the TTL clock source can also be connected directly
to pin 19 (XTAL1). The nominal crystal frequency of most 8051 IC is 12
MHz.
 Memory allocation

• Most microprocessors implement a shared memory space for data

and programs.
• So program usually stored on a disk and loaded into RAM for
execution.
• The both data and program (code) reside into RAM.
• But in case of μ-Controller program reside on ROM (may be EPROM,
FLASH etc) permanent memory where as data exist in the RAM.
• In 89C51 μ-Controller internal code memory is 4K Flash and data
memory is 128 bytes RAM.
• Code Memory and data memory of 8051 μ-Controller can be
extended up to 64K externally by using external components.
64K bytes

64K bytes

256 bytes (Memory)

128 bytes
(SFR)

7F
4K bytes
IRAM
128 bytes

Figure 1
 Program Memory

• Program memory (ROM, EPROM) can only be read,

not written to.
• There can be up to 64k bytes of program memory. In
the 80C51, the lowest 4k bytes of program are on-
chip.
• In the ROMless versions, all program memory is
external.
• The read strobe for external program memory is the
PSEN (program store enable). Figure 1 (left half)
 Data Memory

• Data Memory (RAM) occupies a separate address

space from Program Memory.
• In the 80C51, the lowest 128 bytes of data memory
are on-chip.
• Up to 64k bytes of external RAM can be addressed in
the external Data Memory space.
• The CPU generates read and write signals, RD and
WR, as needed during external Data Memory
accesses. Figure 1 (right half)
 On-Chip Data Memory (RAM)

The 8051’s on-chip memory organized as follows

First 128 bytes (Internal RAM):
• 00h to 1Fh Register Banks
• 20h to 2Fh Bit Addressable RAM
• 30 to 7Fh General Purpose RAM in 8051
• 30 to FFh General Purpose RAM in 8052
Next 128 bytes: 80h to FFh Special Function
Registers
 WHAT ARE SFRS (Special Function Registers)?

• The 8051 is a flexible microcontroller with a relatively large number of

modes of operations.
• Your program may inspect and/or change the operating mode of the 8051
by manipulating the values of the 8051's Special Function Registers
(SFRs).
• 8051 has 21 special function registers (SFRs) at the top of internal RAM
from address 80H to FFH.
• Most of the addresses from 80H to FFH are not defined, except for 21 of
them.
• Accesses to addresses not defined will in general return random data,
and write accesses will have no effect.
• Some SFR’s are both bit-addressable and byte addressable, depending
on the instruction accessing the register
Power Control Register
 Idle Mode

• PCON.0 causes that to be the last instruction executed before

going into the Idle mode.
• The internal clock signal is gated off to the CPU but not to the
Interrupt, Timer, and Serial Port functions.
• The CPU status is preserved in its entirety; the Stack Pointer,
Program Counter, Program Status Word, Accumulator, and all
other registers maintain their data during Idle.
• The port pins hold the logical states they had at the time Idle
was activated. ALE and PSEN hold at logic high levels.
• Idle mode is terminated by any enabled interrupt or by system
reset.
 Power-Down Mode
• An instruction that sets PCON.1 causes that to be the last
instruction executed before going into the Power Down mode.
• In the Power Down mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, the contents of the
on-chip RAM and Special Function Registers are maintained.
• The port pins output the values held by their respective SFRs.
• The ALE and PSEN output are held low.
• The only exit from Power Down is a hardware reset.
• Reset redefines all the SFRs, but does not change the on-chip
RAM.
• In the Power Down mode of operation, VCC can be reduced to as
low as 2V.
 Machine Cycle
• The CPU takes certain number of clock cycles to execute an
instruction. In 8051 these clock cycles are called as machine
cycle.
• One machine cycle lasts 12 oscillator periods means one
machine cycle is 1/12 of crystal frequency.
machine cycle= (1/12) * oscillator periods
Supose find the machine cycle if the oscillator frequency is 24MHz

Machine Cycle= (1/12) *24 MHz

= 2MHz
= 1/2MHz
= 0.5 uSec
 External Memory
• µ-Controller have expansion capabilities beyond the on chip
resources. The MCS-51 architecture provides to expand
memory RAM and ROM up to 64K external space and I/O
capabilities can be enhanced through programmable peripheral
interface (PPI) devices .
• When external memory is used PORT 0 and PORT 2 is not
available as an I/O port.
• It becomes a multiplex address (A0….A7) and data bus (D0…
D7), with ALE latching the low-byte of the address at the
beginning of each external memory cycle.
• PORT 2 is usually employ high-byte of the address bus
External Memory
 Accessing external code memory
• The EA pin is strapped to GND , then all program fetches are
directed to external ROM.
• PSEN, is used for all external program fetches and connected to
the OE pin of ROM.
• Port 0 serves as a multiplexed address/data bus.
• It emits the low byte of the Program Counter (PCL) as an address,
and then goes into a float state awaiting the arrival of the code
byte from the Program Memory.
• The signal ALE clocks this byte into an address latch.
• Meanwhile, Port 2 emits the high byte of the Program Counter
(PCH). Then PSEN strobes the EPROM and the code byte is read
into the microcontroller.
Accessing external code memory

PORT_0 AD0....AD7 D0..D7

74LS373
EA
D
0
Q A0..A7

ALE
G EPROM

PORT_2 A8....A15

PSEN OE

Accessing external code memory

Accessing external code memory
(Timing Diagram)
One Machine Cycle
 Accessing External Data Memory

• External data memory is read/write memory enabled by the RD

& WR signals the alternate pin function of P3.7 and P3.6.
• RAM interface with 8051 is the same way as EPROM’s except
the RD line is connected to the RAM’s output enable OE line
and WR connects to the RAM’s WR line.
• The connections of address and data bus are the same as for
EPROM’s, using PORT 0 and PORT 2.
 Accessing External Data Memory
PORT 0

AD0....AD7 D0..D7

VCC 74LS373

EA

D
Q A0..A7

ALE G
RAM
1K Byte

P2.0 A8
P2.1
A9

NC
PSEN
CS
RD OE
WR WR 0

Accessing external data memory

Timing Diagram
(Read Cycle)
Timing Diagram
(Write Cycle)
Accessing External Code & Data Memory

• If multiple EPROM/EEPROM and/or RAMs are

interfaced to an 8051,address decoding is required.
• If 8K bytes EPROM/RAMs are used, then the address
bus must be decoded to select memory ICs on 8K
boundaries: 0000H-1FFFH.2000H-3FFFH, and so on.
• Typically, a decoder IC such as 74HC138 with its
output connected the chip select (CS) input on the
memory ICs as shown in figure.
 TIMMER OPERATION
• A timer is a series of divide-by-2 flip-flops that receive an input signal as a
clocking source.
• The clock is applied to the first flip-flop, which divides the clock frequency by
2. The output of the first flip-flop clocks the second flip-flop, which also divide-
by-2, and so on. The output of the last stage clocks a timer overflow flip-flop,
or flag, which is tested by software or generates an interrupt.

Q0 Q1 Q2 L o g ic 1 O v e rflo w F L A G
1 = set

D Q

D Q D Q D Q
C lo c k in
Q

Q Q Q C le a r

C lo c k in

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

O v e r flo w F la g

0 1 2 3 4 5 6 7 0

O v e rflo w
C o n d itio n
 TIMMER OPERATION
• Since each successive stage divide-by-2, a timer with n stages
divides the input clock frequency by 2n.
• The 8051 has two internal 16- bit hardware Timer/Counters,
therefore, the 16th or last stage divides the input clock
frequency by 216 = 65,536
• Each Timer/Counter can be configured in various modes,
typically based on 8-bit or 16-bit operation.
• The 8052 product has an additional (third) Timer/Counter.
• The timer can be used as (a) interval timing, (b) event counting,
or (c) baud-rate generation for the built-in serial port.
 Timer special function registers

Timer SFR Purpose Bit-Addressable

TCON Control Yes

TMOD Mode No

TL0 Timer 0 Low-byte No

TH0 Timer 0 High-byte No

TL1 Timer 1 Low-byte No

TH1 Timer 1 High-byte No

 Timer Mode Register

BIT NAME TIMER DESCRIPTION

7 GATE 1 Gate bit, when set, timer only run while INT1 (P3.3 pin)
is high
when 0, timer only run while TR1 bit in TCON is high
6 C/ T 1 Counter/ timer select bit
1 = event counter
0 = interval timer
5 M1 1 Mode bit 1
4 M0 1 Mode bit 0
3 GATE 0 Gate bit, when set, timer only run while INT0 (P3.2 pin)
is high
when 0, timer only run while TR0 bit in TCON is high
2 C/ T 0 Counter/ timer select bit
1 = event counter
0 = interval timer
1 M1 0 Mode bit 1
0 M0 0 Mode bit 0
 Timer modes (M1 & M0 bits)
M1 M0 MODE DESCRIPTION

0 0 0 13-bit timer mode (not generally used in new

design)

0 1 1 16 bit timer/ counter mode

1 0 2 8-bit auto-reload mode

1 1 3 Split timer mode (rarely used)

Timer 0: TL0 is an 8-bit timer controlled by
timer 0 mode bits;
TH0, the same except controlled by timer 1
mode bits, Timer 1 : stopped
16-bit Timer Mode (Mode 1):

Figure: Timer/ Counter 1 Mode 1: 16 bit counter

 16-bit Timer Mode (Mode 1):
• Mode 1 is a 16-bit timer/ counter mode.
• The clock is applied to the combined high and low timer registers (TLx / THx).
• As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. an
overflow occurs on the FFFFh-to-0000H transition of the count and set the timer
overflow flag.
• The overflow flag is the TFx bit in TCON that is read or written by software.
• Normally if the count value is greater than 255, 16-bit timer mode is used.
8-bit Auto-Reload Mode (Mode 2):
 8-bit Auto-Reload Mode (Mode 2):
• Mode 2 is 8-bit auto-reload mode.
• The timer low-byte (TLx) operates as an 8-bit timer while the timer
high-byte (THx) holds a reload value.
• When the count overflows from FFH-to-00H, the timer flag will set,
also the value in THx is loaded into TLx; counting continues from
this value up to the next FFH-to-00H transition, and so on.
• Normally if the count value is less than 255, 8-bit timer mode is
used.
Split Timer Mode (Mode 3):
 Split Timer Mode (Mode 3):

• Mode 3 is the split timer mode and is different for each

timer.
• Timer 0 in mode 3 is split into two 8-bit timers. TL0 and
TH0 act as separate timers with overflows setting the
TF0 and TF1 bits respectively.
• Timer 1 is stopped in mode 3 but can be started by
switching into one of the other modes.
• The only limitation is that the usual timer 1 over flow
flag, TF1, is not effected by timer 1 overflows, since it is
connected to TH0.
 Clocking Source
Interval timing:
• In interval timing C/T = 0, the timer is clocked from the on-chip
oscillator.
• A timer is programmed to overflow at a regular interval and set
the timer overflow flag.
• The flag is used to synchronize the program to perform an
action such as checking the state of inputs or sending data to
outputs.
• In this regard timer can be used to measure the elapsed time
between two condition i.e. pulse width measurements.
 Clocking Source

Event counting
• If C/T = 1, the timer is clocked from external source.
• Event counting is used to determine the number of
occurrences of an event.
• An “event” is any external stimulus that provides a 1-to-0
transition to pins(T0-P3.4 or T1-P3.5) on the 8051 IC.
Baud rate generation
• If C/T = 0, timer is clocked from the on-chip oscillator, can also
provide the baud rate clock for the 8051’s internal serial port.
Symbol Position Description

TF1 TCON.7 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1
overflows. Cleared by hardware as the processor vectors to the
interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn
Timer/Counter 1 ON/OFF.
TF0 TCON.5 Timers 0 overflow flag. Set by hardware when the Timer/Counter
0 overflows. Cleared by hardware as the processor vectors to
the service routine.
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn
Timer/Counter 0 ON/OFF.
IE1 TCON.3 External Interrupt 1 edge flag. Set by hardware when the
External Interrupt edge is detected.
Cleared by hardware when the interrupt is processed.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify
falling edge/low level triggered External Interrupt.

IE0 TCON.1 External Interrupt 0 edge flag. Set by hardware when External
Interrupt edge detected. Cleared by hardware when interrupt is
processed.
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify
falling edge/low level triggered External Interrupt.
Starting, stopping, and controlling
the timers

T im er
Tim er R egister
C lock

0 = U p (tim er stop p ed )
1 = D ow n (tim er start)

TR0 = 1;
TR0 = 0;
 Step to program in mode 1 (16-bit timer)
To generate a time delay, using the timer’s mode 1, the
Following steps are taken,
1. It is the 16-bit timer mode; load the TMOD value register
indicating which timer (timer 0 or timer 1 or both) is to be used.
2. Load registers TL and TH with initial count values.
3. Start the timer.
4. Keep monitoring the timer flag (TF) with while(TF==0) if it is
raised. Take action, and get out of the loop when TF becomes
high.
5. Stop the timer.
6. Clear the TF flag for the next round.
7. Go back to step 2 to load TH and TL again.
• Example: write a program to create 1kHz square wave of 50% duty cycle on P1.0
crystal frequency is 12MHz
Solution:
Calculations: 1kHz=1000uSec
for 50% duty cycle: HT/ON=500uSec, LT/OFF=500uSec
Here Desired Time=500uSec
Timer Clock=cyrstal Freq/12 12Mhz/12= 1Mhz
Timer clock=1/12Mhz= 1uSec
Now divide the desired time delay by timer clock
n=desired time/timer clock=500uSec/1uSec=500
Perform 65536 -n we get 65536 -500=65036 (Timer reload value)
Convert this value in hex that is FE0C
Since the interval is greater than 256uSec so 16 bit timer is used.
So the values for THx=FEh and TLx=0Ch
#include <REGX51.H>
void main()
{
TMOD = 0x01; //timer0,mode1 16bit
while(1)
{
TH0 = 0xFE; //high value of Sq wave=500uSec
TL0 = 0x0C; //500=FE0Ch
TR0=1; //Start timer0
while(TF0!=1) // wait for TF0
{}
TR0=0; //Stop Timer0
TF0=0; //clear TF0
}
}
 Step to program in mode 2 (8-bit timer)
To generate a time delay, using the timer’s mode 2, the following
steps are taken,
1. It is the 8-bit timer mode (auto-reload); load the TMOD value
register indicating which timer (timer 0 or timer 1 or both) is
to be used.
2. Load registers TH with initial count values.
3. Start the timer.
4. Keep monitoring the timer flag (TF) with while(TF==0) if it is
raised. Take action, and get out of the loop when TF
becomes high.
5. Clear the TF flag for the next round.
6. Go back to step 4.
 Basics of serial comunication
• Serial communication standards
RS-485 RS-422 RS-232

Transmitter Receiver

Receiver Transmitter

Half Duplex

Transmitter Receiver
Transmission only
Transmitter Receiver Receiver Transmitter
simplex
Full Duplex
•Asynchronous Serial Communications

Since data is sent is a serial fashion, without any reference to a

timing clock to help synchronize the receiver clock in terms of
frequency and phase, the system is said to be non-
synchronous, or asynchronous.
 Introduction
• The serial port is full duplex (transmission and reception
simultaneous).
• It is also receive-buffered, which means it can begin
receiving a second byte before a previously received byte
has been read from the receive register. (However, if the
first byte still has not been read when reception of the
second byte is complete, one of the bytes will be lost.)
• The serial port receive and transmit registers are both
accessed at Special Function Register SBUF(Serial Buffer).
• Writing to SBUF loads the transmit register, and reading
SBUF accesses a physically separate receive register
 Serial port block diagram

TXD
RXD
(P3.1)
(P3.2)
clk SBUF Q D
Shift register
(write only)
clk
Baud rate
Clock Baud rate
transmit Clock
receive SBUF
(Read only)
 THE 8051 UART

• The 8051 includes a hardware UART to support serial

asynchronous communications so that, typically, the
product can support RS-232 standard communication.
• The UART (Universal Asynchronous Receiver and
transmitter) block diagram is shown in figure. In our
examples the BAUD clocks are, in fact, a single clock
source provided by Timer/Counter 1.
UART block diagram
 9-bit UART
• The UART can be configured for 9-bit data transmission
and reception. Here 8 bits represent the data byte (or
character) and the ninth bit is the parity bit. Figure
shows a block diagram for the UART transmitter, where
the ninth bit is used as the parity bit.
Block diagram of UART receiver, using the 9th. bit
Serial port control register (SCON)
 Serial Mode 0 (8-bit shift register)

One 1
________
Macine Baud - rate
Cycle
Data in
( RXD ) D0 D1 D2 D3 D4 D 5 D6 D 7 Stop
Bit
Shift
Clock
( TXD )

RI =1
SBUF is Full
Figure : Serial port receive timing for mode 0

One 1
________
Macine Baud - rate
Data out Cycle
( RXD )
D 0 D 1 D2 D 3 D4 D 5 D6 D 7 Stop
Bit
Shift
Clock
( TXD )

TI =1
SBUF is
Figure : Serial port Transmits timing for mode 0 Empty
• Mode 0 has a fixed baud rate, which is 1/12 of the oscillator
frequency. To run the serial port in this mode, none of the
Timer/Counters need to be set up. Only the SCON register
needs to be defined.

• One possible application of shift register mode to expand

output capability of 8051. A serial to parallel shift register IC
can be connected to the 8051 TXD and RXD lines to provide
eight output lines
8 extra output
8051
TXD Clk
Shift reg
RXD Data
 Serial mode 1(8-bit mode with variable
Baud Rate)
• 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1).
• On receive, the stop bit goes into RB8 in Special Function
Register SCON. The baud rate is variable.
• In the AT89C51, the baud rate is determined by the Timer 1
overflow rate.
• In the AT89C52 the baud rate is determined either by the Timer
1 overflow rate, the Timer 2 overflow rate, or both. In this case,
one Timer is for transmit, and the other is for receive.
 Serial mode 2(9-bit UART with Fixed
Baud Rate)
• 11 bits are transmitted (through TxD) or received (through RxD):
start bit (0), 8 data bits (LSB first), a programmable 9th data bit,
and a stop bit (1).
• On Transmit, the 9th data bit (TB8 in SCON) can be assigned the
value of 0 or 1. Or, for example, the parity bit (P, in the PSW)
could be moved into TB8.
• On receive,the 9th data bit goes into RB8 in Special Function
Register SCON, while the stop bit is ignored.
• The baud rate is fixed but programmable to either 1/32 or 1/64
the oscillator frequency.
Serial mode 3(9-bit UART with Variable
Baud Rate)
• 11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th
data bit, and a stop bit (1).
• In fact, Mode 3 is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is variable.
NOTE:
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination register. Reception
is initiated in Mode 0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by the incoming start
bit if REN = 1.
 Generating Baud Rates
• Baud Rate in Mode 0

Mode 0 has a fixed baud rate, which is 1/12 of the oscillator frequency. To
run the serial port in this mode, none of the Timer/Counters need to be set
up. Only the SCON register needs to be defined.

• Baud Rate in Mode 1

Mode 1 has a variable baud rate. The baud rate can be generated by either
Timer 1 or Timer 2
Using Timer1 to Generate Baud Rate
• For this purpose, Timer 1 is used in mode 2(Auto-Reload).

Baud Rate = K * Oscillator freq.

32 * 12[256–(TH1)]
if SMOD = 0, then K = 1.
If SMOD = 1, then K = 2. (SMOD is the PCON register).
• Most of the time the user knows the baud rate and needs to
know the reload value for TH1. Therefore, the equation to
calculate TH1 can be written as :

TH1 =256 – K * Oscillator freq.

384 * baud rate

• TH1 must be integer value. Rounding off TH1 to then nearest

integer may not produce the desired baud rate. In this case,
the user may have to choose another crystal frequency.
 Baud Rate in Mode 2
• The baud rate is fixed in this mode and 1/32 or 1/64 of the oscillator
frequency depending on the value of the SMOD bit in the PCON
register.
• In this mode none of the Timers are used and the clock comes
from the internal phase 2 clock.
• SMOD = 1, Baud Rate = 1/32 Osc Freq.
• SMOD = 0, Baud Rate = 1/64 Osc Freq.
• Baud Rate in Mode 3
• The baud rate in mode 3 is variable and sets up exactly the
• same as in mode 1.
Baud Rate Summary
 Programming Steps to transfer data
serially
1. Load TMOD register using timer1 in mode 2
2. TH1 is loaded with selected baud rate value
3. Load SCON register with desired mode
4. Start timer1
5. Character byte is transferred to SBUF (write SBUF)
6. Monitor the TI
7. Clear TI
8. To transfer the next character, go to step5
• write a program to transfer a letter ‘Y’ serially at 9600 baud rate continuously, and also
send a letter ‘N’ through port 0, which is connected to a display device
#include <AT89X51.H>
void main (void)
{
TMOD=0x20;
TH1=0xF9; //baud rate 9600 crystal = 12Mhz
SCON=0x50; // mode1
TR1=1;
while(1)
{
SBUF=‘Y';
while(TI==0)
{}
TI=0;
}
}
Write a program to receive the data which has been sent in serial form and
send it out to port0 . Also save the data

#include <AT89X51.H>
void main (void)
{ unsigned cha MyByte;
TMOD=0x20;
TH1=0xFD; //baud rate 9600 crystal = 11.059Mhz
SCON=0x50; // mode1
TR1=1;
while(1)
{ RI=0;
while(RI==0)
MyByte = SBUF;
P0= MyByte ;
}
}
 RS 232 (Serial Port)
IBM PC DB – 9 Signal

Pin# Description
1 Data Carrier Detect
TxD RxD
(DCD)
RxD TxD
2 Received Data (RxD)
Ground 3 Transmitted Data (TxD)
4 Data Terminal Ready
(DTR)
5 Signal grounding (GND)
6 Data Set Ready (DSR)
7 Request To Send (RTS)
8 Clear to Send (CTS)
9 Ring Indicator (RI)
 Interrupt
• An interrupt is the occurrence of a condition; an
event that cause a temporary suspension of a
program whiles the condition is serviced by another-
program.
• When an interrupt occurs, the main program
temporarily suspends execution and branches to the
ISR.
• The program that deals with an interrupt is called an
interrupt service routine (ISR) or interrupt handler.
• There are five interrupt sources on the 8051; two
external interrupts, two timer interrupts, and a serial
port interrupt.
 IE (Interrupt enable register)

Table: IE (Interrupt enable register)

EA --- ET2 ES ET1 EX1 ET0 EX0

Symbol Position Description

EA IE.7 Global enable/disable.

--- IE.6 Undefined/reserved.

ET2 IE.5 Timer 2 Interrupt enable bit (AT89C52).

ES IE.4 Serial Port Interrupt enable bit.

ET1 IE.3 Timer 1 Interrupt enable bit.

EX1 IE.2 External Interrupt 1 enable bit.

ET0 IE.1 Timer 0 Interrupt enable bit.

EX0 IE.0 External Interrupt 0 enable bit.

Over view of 8051 interrupt
structure.
 To enable any individual interrupt:
• For example, Timer1 interrupts are enabled as follows;
SETB ET1 ; Enable Timer1 interrupt
SETB EA ; Set global Enable bit
OR
MOV IE, #10001000B
IN C
ET1=1;
EA=1
OR
IE=0x88;
 Interrupt Priority
• Each interrupt source is individually programmed to one of two
priority levels through the bit-addressable special function
register IP (Interrupt priority).
• After system reset IP is cleared to place all interrupts at the
lower priority level by default.
Table: IP (Interrupt priority register)

--- --- PT2 PS PT1 PX1 PT0 PX0

Symbol Position Description

-- IP.7 reserved

--- IP.6 reserved

PT2 IP.5 Timer 2 Interrupt priority bit.

PS IP.4 Serial Port Interrupt priority bit.

PT1 IP.3 Timer 1 Interrupt priority bit.

PX1 IP.2 External Interrupt 1 priority bit

PT0 IP.1 Timer 0 Interrupt priority bit.

PX0 IP.0 External Interrupt 0 priority bit.

 Polling sequence
• If two interrupts of same priority occur simultaneously, a fixed pooling
sequence determines which is served first.
• The polling sequence is external 0, timer 0, external 1, timer 1, serial
port, timer 2.

Interrupt Source Priority with in level

No.
0 IE0 (External 0) Highest
1 TF0 (Timer 0)
2 IE1 (External 1)
3 TF1 (Timer 1)
4 RI + TI (Serial communication)

5 TF2 + EXF2 (Timer2) Lowest

 Processing Interrupts
When an interrupt occurs and is accepted by the CPU,
the main program is interrupt. The following actions
occur:
1. The current instruction completes execution.
2. The PC (address of the next instruction) is saved on
the stack
3. The current interrupt status is saved internally
4. The PC is loaded with the vector address of the ISR
5. The ISR executes.
6. The ISR finishes with a RETI (return from
interrupt) instruction.
 Interrupt Vectors
• When an interrupt is accepted, the value loaded into
the PC is called the interrupt vector. It is the address
of the start of the ISR for the interrupt source.
• When “vectoring to an interrupt,” the flag that
caused the interrupt is automatically cleared by
hardware. The exceptions are RI and TI for Serial
port interrupts, and TF2 and EXF2 for Timer2
interrupt.
 Interrupt Vector Table

Interrupt Source Flag or Port Pin Vector Address

System Reset RST Pin 0000h

External 0 IE0 0003h

Timer 0 TF0 000Bh

External 1 IE1 0013h

Timer 1 TF1 001Bh

Serial Port RI or TI 0023h

Timer 2 TF2 or EXF2 002Bh

 Small interrupt service
routine
• Interrupt service routine is always begin
near the bottom of the code memory at the
address shown in the above vector table.
• Since there are only 8 bytes between each
interrupt entry point, so if ISR is such that
it accommodate with in 8-bytes then small
interrupt service routine could be used
ORG 0000H ; Reset entry point
LJMP MAIN
ORG 0003H ; External 0 ISR entry point …………………. ; code
RETI
ORG 000BH ; Timer 0 ISR entry points …………………. ; code
RETI
ORG 0013H ; External 1 ISR entry points …………………. ; code
RETI
ORG 001BH ; Timer 1 ISR entry points …………………. ; code
RETI
ORG 0023H ; Serial comm. ISR entry points …………………. ; code
RETI
ORG 0030H ; Main program entry point
MAIN:
…………………. ; code
…………………. ; code
END
 Large interrupt service
routine
If the ISR contains more than 8 bytes then large interrupt service routine must be use.
ORG 0000H ; Reset entry point
LJMP MAIN
ORG 0003H ; External 0 ISR entry points
LJMP EXT0ISR
ORG 000BH ; Timer 0 ISR entry points
LJMP T0ISR
ORG 0030H ; Main program entry point
MAIN:
…………………. ; code
…………………. ; code
EXTOISR
…….. ; External 0 ISR
RETI
TOISR
…….. ; Timer 0 ISR
RETI
END
#include <AT89X51.H>
void main (void)
{
main body............
}
void EXTERNAL0 (void) interrupt 0
{
}
void Timer0 (void) interrupt 1
{
}
void EXTERNAL1 (void) interrupt 2
{
}
void Timer1 (void) interrupt 3
{
}
void Serial(void) interrupt 3
{
}
 Example: writ a program using timer 0 and interrupts to create a 10-KHz
square wave on P1.0 bit of 89C51 IC.

ORG 00H ; Reset entry point

LJMP MAIN
ORG 000BH ; Timer 0 interrupt entry point
CPL P1.0 ; toggle port bit
RETI
------------------------------------------------------------------------------
ORG 0030H
MAIN:
MOV TMOD, #02H ; Timer 0 mode 2
MOV TH0, # CEH ; 50 u-sec delay
SETB TR0 ; Run Timer 0
MOV IE, #82H ; enable timer 0 interrupt
LOOP:
SJMP LOOP
#include <AT89X51.H>
sbit x=P2^1;
void main (void)
{
TMOD=0x02; //Timer1 in mode
IE=0x82;
TH0=0xCE;
TR0=1;
while(1)
{}
}
void timer0 (void)interrupt 1
{
x=~x;
}
 External Interrupts
• External interrupts occur as a result of a low-level or negative
edge on the INT0 or INT1 pin on the 8051 IC.
• These are the alternate function for Port 3 bits P3.2 and P3.3
respectively.
• The flags that actually generate these interrupt are bits IE0 and IE1
in TCON register.
• The external interrupts can be configured as low-level activated
interrupt or negative edge-trigger activated interrupt, this can be
program through IT0 and IT1 bits in TCON register.
• If IT0 = 0 than external interrupt 0 is triggered by detecting low-
level at the INT0 pin.
• If IT0 = 1 than external interrupt 0 is triggered by detecting
negative-edge at the INT0 pin.
• Low-level activated interrupt:In case of low-
level activated interrupt, external requesting
source controls the level of the request flag,
rather than the on chip hardware
• Negative edge trigger activated interrupt:
In case of negative edge trigger interrupt, when
ever high to low transition occur in respective
interrupt pin than an external interrupt is
generated, the flag that generated it is cleared
by hardware when vectoring to the ISR.
 Interrupt latency
• The time between an interrupt condition
occurring and the ISR beginning is called
interrupt latency.
• With a 12-MHz crystal, the interrupt latency
can be as short as 3.25 u-sec on the 8051.
An 8051 system that uses one high-priority
interrupt will have a worst-case interrupt
latency of 9.25 u-sec.
 Start Ground Ground Ground Ground
First 2 nd 3 rd Fourth
Column Column Column Column

Ground all Wait for Wait for Wait for Wait for
Columns key key key key
denounce denounce denounce denounce

Wait for
key Read all Read all Read all Read all
denounce Rows Rows Rows Rows

Read all NO NO
NO
Rows
which key is which key is which key is which key is
pressed ? pressed ? pressed ? pressed ?
NO '1 ','4','7','A' ''2 ','5','8','0 ' '3 ','6 ','9 ','B' 'F','E','D','C '
All keys
open ? YES YES YES YES

YES Return Return Return Return

match KEY match KEY match KEY match KEY
Return
KEY = ’Q’

Figure . KEY 4 X 4 Scan Flow Chart Return

KEY = ’Q’
 Figure . KEY 4X4 Scan Hardware

VCC
10 nF

10 K 1 2 3 F
P2.4
10nF 4 5 6 E
VCC
INPUT

10K
P2.5 7 8 9 D
10nF
VCC

A 0 B C
10K

P2.6 10nF
VCC

10K
P2.7
P2.0 P2.1 P2.2 P2.3

OUTPUT
Basics of serial comunication