Digital Integrated Circuits © Prentice Hall 1995 Design Methodologies

Digital Integrated Circuits Prentice Hall 1995 Design Methodologies
Design
Methodologies
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
Design Methodology
Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
More and more automation for each of these steps
Design Analysis and Verification
Accounts for largest fraction of design time
More efficient when done at higher levels of
abstraction - selection of correct analysis
level can account for multiple orders of
magnitude in verification time
Two major approaches:
Simulation
Verification
Digital Data treated as Analog Signal
V
o
u
t

(
V
)
5.0
3.0
1.0
1.0
t (nsec)
2 1.5 1 0. 5 0
Vin Vout
t pHL
Gn,p
In Out
VDD
Bp
Bn
Dn,p
Sn
Sp
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation)
Representing Data as Discrete Entity
V
t
V
M
t
1
t
2
0 1 0 V
DD
R
n
R
p
C
L
Discretizing the data using
switching threshold
The linear switch model
of the inverter
Circuit versus Switch-Level Simulation
0 5 10 15 20
time (nsec)
1.0
1.0
3.0
5.0
CI N
OUT[3]
OUT[2]
C
i
r
c
u
i
t

S
w
i
t
c
h

Structural Description of Accumulator
entity accumulator is
port ( --
definition of input and output terminals
DI: in bit_vector(15 downto 0) --
a vector of 16 bit wide
DO: inout bit_vector(15 downto 0);
CLK: in bit
);
end accumulator;
architecture structure of accumulator is
component reg --
definition of register ports
port (
DI : in bit_vector(15 downto 0);
DO : out bit_vector(15 downto 0);
CLK : in bit
);
end component;
component add --
definition of adder ports
port (
IN0 : in bit_vector(15 downto 0);
IN1 : in bit_vector(15 downto 0);
OUT0 : out bit_vector(15 downto 0)
);
end component;
--
definition of accumulator structure
signal X : bit_vector(15 downto 0);
begin
add1 : add
port map (DI, DO, X); --
defines port connectivity
reg1 : reg
port map (X, DO, CLK);
end structure;
Design defined as composition of
register and full-adder cells (netlist)

Data represented as {0,1,Z}

Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog
Behavioral Description of Accumulator
entity accumulator is
port (
DI : in integer;
DO : inout integer := 0;
CLK : in bit
);
end accumulator;
architecture behavior of accumulator is
begin
process(CLK)
variable X : integer := 0; --
intermediate variable
begin
if CLK = '1' then
X <= DO + D1;
DO <= X;
end if;
end process;
end behavior;
Design described as set of input-output
relations, regardless of chosen
implementation

Data described at higher abstraction
level (integer)
Behavioral simulation of accumulator
Integer data
Discrete time
(Synopsys Waves display tool)
Timing Verification
(Synopsys-Epic Pathmill)
Critical path
Enumerates and rank
orders critical timing paths

No simulation needed!
Issues in Timing Verification
bypass
4-bit adder
M
U
X
Out
In
False Timing Paths
Implementation Methodologies
Digital Circuit Implementation Approaches
Custom
Semi-custom
Cell-Based
Array-Based
Standard Cells
Macro Cells Pre-diffused Pre-wired
(FPGA)
Compiled Cells
(Gate Arrays)
Custom Design
Layout Editor
Magic Layout Editor
(UC Berkeley)
Symbolic Layout
1
3
In
Out
V
DD
GND
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by
compaction program
Cell-based Design (or standard cells)
Functional
Module
(RAM,
multiplier, )
R
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s

o
f

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l
s
Logic Cell
Routing
Channel
Feedthrough Cell
Routing channel
requirements are
reduced by presence
of more interconnect
layers
Standard Cell Example
[Brodersen92]
Standard Cell - Example
3-input NAND cell
(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies
Automatic Cell Generation
Random-logic layout
generated by CLEO
cell compiler (Digital)
Module Generators
Compiled Datapath
a
d
d
e
r
b
u
f
f
e
r
r
e
g
0
r
e
g
1
m
u
x
bus0
bus2
bus1
bit-slice
routing area
feed-through
Advantages: One-dimensional placement/routing problem
Macrocell Design Methodology
Macrocell
Interconnect Bus
Routing Channel
Floorplan:
Defines overall
topology of design,
relative placement of
modules, and global
routes of busses,
supplies, and clocks
Macrocell-Based Design
Example
Video-encoder chip
[Brodersen92]
SRAM
SRAM
Data paths
Standard cells
Gate Array Sea-of-gates
rows of
cells
routing
channel
uncommitted
VDD
GND
polysilicon
metal
possible
contact
In1 In2 In3 In4
Out
Uncommited
Cell
Committed
Cell
(4-input NOR)
Sea-of-gate Primitive Cells
NMOS
PMOS
Oxide-isolation
PMOS
NMOS
NMOS
Using oxide-isolation Using gate-isolation
Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 mm CMOS)
Prewired Arrays
Categories of prewired arrays (or field-
programmable devices):
Fuse-based (program-once)
Non-volatile EPROM based
RAM based
Programmable Logic Devices
PLA PROM
PAL
EPLD Block Diagram
Macrocell
Courtesy Altera Corp.
Primary inputs
Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
I/O Buffers
I
/
O

B
u
f
f
e
r
s
I
/
O

B
u
f
f
e
r
s
Vertical routes
Rows of logic modules
Routing channels
Standard-cell like
floorplan
Interconnect
Cell
Horizontal
tracks
Vertical tracks
Input/output pin
Antifuse
Programmed interconnection
Programming interconnect using anti-fuses
Field-Programmable Gate Arrays
RAM-based
CLB CLB
CLB
CLB
switching matrix
Horizontal
routing
channel
Vertical routing channel
Interconnect point
RAM-based FPGA
Basic Cell (CLB)
R
Q1 D
CE
R
Q2 D
CE
F
G
F
G
F
G
R
D
in
Clock
CE
F
G
A
B/Q1/Q2
C/Q1/Q2
D
A
B/Q1/Q2
C/Q1/Q2
D
E
Combinational logic Storage elements
Any function of up t o
4 variables
Any function of up t o
4 variables
Courtesy of Xilinx
RAM-based FPGA
Xilinx XC4025
Taxonomy of Synthesis Tasks
Architectural Level Logic Level Circuit Level
B
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a
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a
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V
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Architecture
Synthesis
Logic
Synthesis
Circuit
Synthesis
0
1
3
2
state
(i: 1..16) ::
sum = sum*z
1
+
coeff[i]*In*z
1
a
b
c
x
a
b
c
1
2
2
4
t
p
a
b
c
x
D
mem
*
fsm
Design
for Test
Validation and Test of
Manufactured Circuits
Components of DFT strategy
Provide circuitry to enable test
Provide test patterns that guarantee reasonable
coverage
Goals of Design-for-Test (DFT)
Make testing of manufactured part swift and
comprehensive
DFT Mantra
Provide controllability and observability
Test Classification
Diagnostic test
used in chip/board debugging
defect localization
go/no go or production test
Used in chip production
Parametric test
x e [v,i] versus x e [0,1]
check parameters such as NM, V
t
, t
p
, T
Design for Testability
M state regs
N inputs
K outputs
K outputs N inputs
Combinational
Logic
Module
Combinational
Logic
Module
(a) Combinational function
(b) Sequential engine
2
N
patterns 2
N+M
patterns
Exhaustive test is impossible or unpractical
Problem:
Controllability/Observability
Combinational Circuits:
controllable and observable - relatively easy to
determine test patterns
Sequential Circuits: State!
Turn into combinational circuits or use self-test
Memory: requires complex patterns
Use self-test
Test Approaches
Ad-hoc testing
Scan-based Test
Self-Test
Problem is getting harder
increasing complexity and heterogeneous
combination of modules in system-on-a-chip.
Advanced packaging and assembly techniques
extend problem to the board level
Generating and Validating
Test-Vectors
Automatic test-pattern generation (ATPG)
for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output
majority of available tools: combinational networks only
sequential ATPG available from academic research
Fault simulation
determines test coverage of proposed test-vector set
simulates correct network in parallel with faulty networks
Both require adequate models of faults in
CMOS integrated circuits
Fault Models
0
1
sa0
sa1
(output)
(input)
Most Popular - Stuck - at model
x1
x2
x3
Z
, : x1 sa1
: x1 sa0 or
x2 sa0
: Z sa1
Covers almost all (other)
occurring faults, such as
opens and shorts.
Problem with stuck-at model:
CMOS open fault
x1
x2
x1
x2
Z
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short models
This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
Problem with stuck-at model:
CMOS short fault
0
0
0
1
C
A B
D
A
B
C
D
Causes short circuit between
Vdd and GND for A=C=0, B=1

Possible approach:
Supply Current Measurement (IDDQ)
but: not applicable for gigascale
integration
Path Sensitization
Out
Techniques Used: D-algorithm, Podem
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
sa0
1
1
0
1
1
1
0
1
Fault propagation
Fault enabling
Ad-hoc Test
Inserting multiplexer improves testability
I/O bus
Memory
Processor
d
a
t
a
a
d
d
r
e
s
s
I/O bus
Memory
Processor
d
a
t
a
a
d
d
r
e
s
s
select
test
Scan-based Test
Logic
Combinational
Logic
Combinational
R
e
g
i
s
t
e
r
R
e
g
i
s
t
e
r
Out
In
ScanOut
ScanIn
A B
Polarity-Hold SRL
(Shift-Register Latch)
Introduced at IBM and set as company policy
System Data
System Clock
Scan Data
Shift A Clock
D
C
SI
A
L1
L2
Shift B Clock
B
Q
Q
SO
SO
Scan-Path Register
SCANIN
IN
LOAD
SCAN PHI2 PHI1
KEEP
OUT
SCANOUT
Scan-based Test Operation
Test
ScanIn
Test
Latch
In
0
Out
0
Test Test
Latch
In
1
Out
1
Test Test
Latch
In
2
Out
2
Test Test
Latch
In
3
Out
3
ScanOut
Test
2
N cycles
1 cycle
evaluation
scan-in
N cycles
scan-out
Scan-Path Testing
Partial-Scan can be more effective for pipelined datapaths
REG[5]
REG[4]
REG[3] REG[2]
REG[0] REG[1]
+
COMP
OUT
SCANIN
COMPIN
SCANOUT
A B
Boundary Scan (JTAG)
Printed-circuit board
Logic
scan path
n
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t
Packaged IC
Bonding Pad
Scan-in
Scan-out
si so
Board testing becomes as problematic as chip testing
Self-test
(Sub)-Circuit
Under
Test
Stimulus Generator Response Analyzer
Test Controller
Rapidly becoming more important with increasing
chip-complexity and larger modules
Linear-Feedback Shift Register (LFSR)
S
0
S
1
S
2
R R R
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0
Pseudo-Random Pattern Generator
Signature Analysis
R
Counter
In
Counts transitions on single-bit stream
Compression in time
BILBO
S0
R R R
S1 S2
ScanOut ScanIn
m
u
x
D2 D1 D0
B0
B1
Operation mode B
0

Normal
Scan
Signature analysis
1 1
0 0
1 0
Pattern generation or
0 1 Reset
B
1
BILBO Application
Logic
Combinational
Logic
Combinational
B
I
L
B
O
-
B
B
I
L
B
O
-
A Out
In
ScanIn ScanOut
Memory Self-Test
FSM
Memory Signature
Analysis
Under Test
data
address &
R/W control
-in
data-out
Patterns: Writing/Reading 0s, 1s,
Walking 0s, 1s
Galloping 0s, 1s

Digital Integrated Circuits © Prentice Hall 1995 Design Methodologies

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