Topics

● PDP-8 datapath design.

● 8086 datapath design issues.

Computing Structures © 1998 W. Wolf CPU organization

 Datapath design issues

● Must include architected registers.

● Must supply data paths for required transfers.
● Must support hidden operations:
- indirection;
- autoincrementing.

Computing Structures © 1998 W. Wolf CPU organization

 PDP-8 front panel
memory address

instruction memory contents

link accumulator run

switch register

start deposit examine continue

stop s step

Computing Structures © 1998 W. Wolf CPU organization

 PDP-8 instructions

and logical AND.

tad two's-complement add.
isz increment and skip if 0.
dca deposit and clear AC.
jmp jump.
jms jump to subroutine.
group 1 microinstructions clear, increment, rotate, skip, halt.
group 2 microinstructions skip on conditions.

Computing Structures © 1998 W. Wolf CPU organization

 Architecture definition

Some operations and registers are defined in the machine

specification:
- PC is an architected register;
- effects of TAD on PC, AC, Link are defined.
Some operations and registers are internal:
- MA, MB are not fully defined in the architecture;
- number of clock cycles per instruction is not defined.

Computing Structures © 1998 W. Wolf CPU organization

 Design
strategy
Think of datapath as a data structure used by control program:

link

registers ALU

external

Computing Structures © 1998 W. Wolf CPU organization

 Architected
registers

AC accumulator.
Link arithmetic overflow.
MA memory address.
MB value to be read/written from/to memory.
PC program counter.
IR instruction register.

Computing Structures © 1998 W. Wolf CPU organization

 Accumulator data
paths
iac, tad, and, osr all require the same basic data paths:

AC

ALU

other operand

Computing Structures © 1998 W. Wolf CPU organization

 PC data paths
PC must be incremented during normal operation---use ALU.
PC must also be loaded.

+1

ALU

PC

Computing Structures © 1998 W. Wolf CPU organization

 Operands from
memory
Operands from memory can be fed directly into the datapath:

AC

MA
ALU
adrs
memory out
in

MB

Computing Structures © 1998 W. Wolf CPU organization

 Other operations

Instruction can be loaded through ALU bus.

Make AC and link into a 12-bit shift register for shift
operations.

Computing Structures © 1998 W. Wolf CPU organization

 Basic data
AC
path ALUBUS
MA

MEM
ALU

MB

PC
EA
op
IR SR select

Computing Structures © 1998 W. Wolf CPU organization

 Instruction fetch
ALUBUS
AC

MA

MEM
ALU

MB

PC
EA
MUX
IR SR PC

Computing Structures © 1998 W. Wolf CPU organization

 Data
AC
fetch ALUBUS
MA

MEM
ALU

MB

PC
EA
MUX
IR SR EA

Computing Structures © 1998 W. Wolf CPU organization

 Addition
ALUBUS
AC

MA

MEM
ALU

MB

PC
EA
+
IR SR MB

Computing Structures © 1998 W. Wolf CPU organization

 Incremen
AC
t ALUBUS
MA

MEM
ALU

MB

PC
EA
+1
IR SR X

Computing Structures © 1998 W. Wolf CPU organization

 Sources of parallelism

Across the CPU: simultaneous fetch/execute.

Within the CPU:
- busses;
- extra function units;
- match of function units to required operations.

Computing Structures © 1998 W. Wolf CPU organization

 Bus parallelism and
registers
Fewer busses means fewer register accesses---temporaries, more
cycles:

registers func registers f

three-port one-port

Computing Structures © 1998 W. Wolf CPU organization

 Register
files
Register files are usually built from SRAMs.
Each port has its own word, bit lines:

w0w1w2

core
bit0
bit1
bit2

Computing Structures © 1998 W. Wolf CPU organization

 Shifter
s
Can make AC from parallel-load shift register:

Can build combinational shifter in datapath:

out3
in3
out2
in2
in1 out1
in0 0 out0

Computing Structures © 1998 W. Wolf CPU organization

 Microinstructions
Skip requires two cycles:
- run accumulator through ALU to generate status bits;
- depending on result, add 1 to PC.
Rotate with link: link
- recirculate shift line;
2901
- two-bit rotate takes two cycles.
Access to registers for front panel? 2901

2901

Computing Structures © 1998 W. Wolf CPU organization

 8086
datapath

● Multiple registers.

● Variable length instructions.

● More addressing modes.

● Memory mapping requires extensive address arithmetic.

● Status word.

Computing Structures © 1998 W. Wolf CPU organization

 Register
bank
Move instruction dictates that any pair of registers must be
transferrable:

registers ALU temp

Computing Structures © 1998 W. Wolf CPU organization

 One-port register file
Fewer register ports requires more temporary registers, more cycles:

registers ALU temp

Computing Structures © 1998 W. Wolf CPU organization

 Multiple-word instructions

Opcode is completely contained in first word. Successive bytes

contain: data, postbyte, address, displacement, port.
Postbyte, displacement, immediate, port may be kept in temporary
registers---don't need to explicitly keep original instruction.
Requires multiple PC increments.

Computing Structures © 1998 W. Wolf CPU organization

 Address
arithmetic
Based, indexed, relative addressing each require one addition.
Relative addressing requires PC to be on same datapath as registers.
Based indexed addressing requires three additions: base register,
index register, offset. Do we need multiple adders?

MAR reg ALU add add

displacement

Computing Structures © 1998 W. Wolf CPU organization

 Status logic

Logic outboard of ALU computes status codes on every operation.

Status bits should be loaded only on relevant operations.

load
A status
logic flags

ALU

B
result

Computing Structures © 1998 W. Wolf CPU organization