CENTRAL PROCESSING

UNIT
Topics

Components
Control unit (CU)
Arithmetic logic unit (ALU)
Registers

Memory
Main memory
Secondary memory

Input/Output devices
Bus interconnection
Instruction-Execute Cycle
Modern Processors
COMPONENTS
All computers has two basic components
Primary storage or memory
Central processing unit or CPU
The CPU is the Brain of the computer

The CPU Executes programs stored in main
memory
Fetch instructions
Interpret instructions
Process data
Write data

The CPU needs
Control Unit
Arithmetic Logic Unit (ALU)
Registers
CPU STRUCTURE
Topics

Instruction Decoder
IR MAR
MBR
PC
DR
Arithmetic Logic Unit
AC MQ
MM
PSW
I/O Module

I/O
Module
Control Unit (CU)
Circuitry located on the CPU
Coordinates and control all h/w
Controls the operation of the ALU

Responsible for
Fetching instructions
Decoding the instructions
Arithmetic Logic Unit
(ALU)
Does the actual computation
Performs the arithmetic and / or logic operation
Most of the operations require two operands
Operates only on data in the internal CPU
memory
Arithmetic operations
Addition
Subtraction
Multiplication
Division
Basic logic functions
And
Or
Not
Registers
Smallest units of memory

An internal CPU memory

Fastest and most expensive memory

Store temporary results or control information

2 functions :
user-visible registers
Referenced by means of the
machine language
Example :
General Purpose Registers
Registers
Control and status registers
To control the operation of the CPU
Are not visible to the user
With predefined functions
Example :
Program Counter (PC)
Instruction Registers (IR)
Memory Address Registers (MAR)
Memory Buffer Registers (MBR)
Program Counter (PC)
Program Status Word (PSW)
MEMORY
Storage for programs and data

Basic unit of memory is the binary
digit, bit made up of zeros and ones.

Consist of a number of locations
each can store a piece of
information (a word)

Each Byte in memory (location) has
a unique address

Often referred to as random access
memory (RAM)
MEMORY
Memory organisation:








This memory is called a N-word m-
bit memory
N generally is in a power of 2,
i.e. N = 2
n

Size of address is n bits
Size of word is m bits
Example : A 4096-word 16-bit
memory
Word Length = M bits
. .
.
.
. .
N words
Bit 1
Bit 2
Address 0
Address 1
Address 2
Address N-2
Address N-1
MEMORY







Memory access
CPU communicates with main
memory via the MAR, MBR
and the Read/Write control
lines
Word Length = m bits
. .
.
.
. .
N words
Address 0
Address 1
Address 2
Address 2
12
-2
Address 2
12
-1
MEMORY









Memory read
Address is placed into MAR
Read control line is asserted
Content of desired location is placed into
MBR
Word Length = M bits
. .
.
.
. .
Uni-directional
address bus
Address 0
Address 1
Address 2
Address N-2
Address N-1
n bits
M
A
R
MBR
m bits
Bi-directional
data bus
MEMORY
Memory write

The word to be written is placed
into MBR

Address of memory location to be
written is specified in MAR

Write control line is asserted

Content of MBR is transferred into
memory location specified by MAR
INPUT / OUTPUT DEVICES
Input Devices
Accepts outside information
Converts it into digital pulses
suitable for computation by the CPU

Output Devices
Communicates data stored in
memory or processed data, to the
outside world
May be in various forms such as
visual display screen or a hardcopy
BUS INTERCONNECTION
A bus is a communication
pathway connecting two or more
devices
It is a shared transmission
medium
Only one device at a time can
successfully transmit
Consist of multiple
communication pathways, or lines
Connects major computer
components (CPU, CU, I/O)

BUS INTERCONNECTION
Bus Structure

A system bus typically consists of
50-100 separate lines

Each line is assigned to a particular
meaning or function
BUS INTERCONNECTION
The bus lines can be classified into 3
functional group
Data lines
Provide a path for moving data between
system modules
Typically consists of 8, 16, 32 separate
lines
The number of lines being referred to as
the width o the data bus
The width also determines how many bits
can be transferred at a time, key factor in
determining overall system performance
BUS INTERCONNECTION
Address lines
Used to designate the source the source
or destination of the data on the data bus
The width of the address bus determines
the maximum possible memory capacity
of the system
BUS INTERCONNECTION
Control Lines
Used to control the access to and the use
of data and address lines
Control signals transmit both command
and timing information between system
modules
Timing signals indicate the validity of data
and address information
Command signals specify the operations
to be performed
BUS INTERCONNECTION
If one module wishes to send data
to another, it must:
obtain the use of the bus
transfer data

If one module wishes to grant data
from another module, it must:
obtain the use of the bus
transfer a request to the other module
wait for that second module to send
the data
INSTRUCTION-EXECUTE
CYCLE
All computers have an instruction-Execute cycle
A basic Instruction-Execute cycle consist of two steps:
Fetch cycle
Execute cycle
Fetch cycle

Step :
1. [PC] [MAR]
2. [MAR] Address Bus
3. Read control line is asserted
4. [MEM] Data bus [ MBR]
5. [MBR] [IR]
6. [PC] + 1 [PC]
FETCH-EXECUTE CYCLE
Execute cycle
Steps :
1. [IR] decoding circuitry
2. If required data are not available in
instruction, determine the location
3. Fetch the data, if any
4. Execute results, if any
5. Store results, if any
The actions within the execution cycle can be
categorized in to the following four groups:
1. CPU Memory
2. CPU I/O
3. Data Processing
4. Control
Example
Draw a diagram (includes MAR, MBR, IR and PC),
show how the instruction MOV AX, [7000] is
being fetched if the starting address for the
instruction is 1FFF and the content of the
location at 7000 is ABCD.

INSTRUCTION - FETCH
CYCLE











C & D C = Control and Decoding
Circuitry
1 FFF
MOV AX, [7000] MOV AX, [7000]
1FFF
ABCD
MOV AX, [7000]
7000
1FFF
(4a)
(5)
(6) [PC] [PC] + 1
Address
Bus
Data Bus
(3) Assert Read
Line
(4b)
IR MBR
PC MAR
(1)
(2)
Memory
EXECUTE CYCLE
MOV AX, [7000]
(2c)
Read Line
7000
ABCD
IR
Decoding circuitry
(1)
7000
ABCD
ABCD
AX
MAR
MBR
(2a)
(3b)
(2b)
(3a)
Address Bus
(4)
Data Bus
FETCH-EXECUTE CYCLE
Instruction-fetch-cycle:
1. [PC] [MAR] MAR = 1FFF
2. [MAR] Address Bus
3. READ control line is asserted
4. [Memory]
1FFF
Data Bus [MBR]
MBR = MOV AX, [7000]
5. [MBR] [IR] IR = MOX AX, [7000]
6. [PC] + 1 [PC] PC = 2000
Execute-cycle:
1. [IR] decoding circuitry MAR = 7000
2. [MAR] 7000
[MAR] Address Bus
READ control line is asserted
3. [Memory]
7000
Data Bus [MBR]
MBR = ABCD
4. [MBR] AX AX = ABCD
INTERRUPT CYCLE
An interrupt can be described as a mechanism in
which an I/O module etc. can break the normal
sequential control of the central processing unit
(CPU). And thus alter the way we view the
traditional sequence of the fetch and execute cycle.



Fetch Cycle

Execute Cycle
Disabled Enabled
Interrupt Cycle
Common interrupts that the CPU can receive
Program
Timer
I/O
Hardware failure

Start
Fetch instruction
Execute
instruction
Check for interrupt
Halt
MODERN PROCESSORS

Cycle 1 Cycle 2 Cycle 3 Cycle 4
Instruction 1 Fetch Execute
Instruction 2 Fetch Execute

Sequential execution of program instructions


Cycle 1 Cycle 2 Cycle 3 Cycle 4
Instruction 1 Fetch Execute
Instruction 2 Fetch Execute
Instruction 3 Fetch Execute

Execution cycle in a three-stage pipelined
processor

EXERCISES
1. Show the fetch and execute cycle
for the instruction ADD [1000],
[2000], [3000] which will add two
numbers in memory location
1000 and 2000, then store the
result at location 3000.





2. Show the sequences of the fetch
and execute cycle for question 1 if
the instruction is changed to MOV
[1000], [3000]. That is, moving
the content in memory location
3000 to memory location 1000.
ABCD
2FEE
DEAD
1000
2000
3000
EXERCISES
3. The instruction LOA LABEL
moves the content at address
LABEL (hexadecimal) into the
AX register. The opcode and the
main memory is 1 byte wide,
while the address is 2 bytes
wide.

a. With the aid of a diagram,
show how the
instruction LOA [9000] is loaded
into the main
memory if the starting address
for the instruction is 2512
and the content of the
location 9000 is FIFO.
b. Describe the sequence of
events for the
instruction-fetch-cycle for the
above instruction.
c. Describe the sequence of
events for the
execute-cycle for the above
instruction.