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Algorithm and
Parameters
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Contents
1. Power Control Overview
2. HW Power Control Algorithm
3. HW Power Control Algorithm
4. Other Algorithms
Page1
Power control
Purpose
Page2
Page3
SA0
SA0 SA1
In the 26 multi-frames,
frame 12 sends
SACCH.
MS obtains SACCH
block
Page4
Page5
Page6
Data Configuration of MR
Preprocessing
Page7
Page8
Contents
1. Power Control Overview
2. HW Power Control Algorithm
3. HW Power Control Algorithm
4. Other Algorithms
Page10
HW II Power Control
Page11
HW II Power Control
BTS
Network
Downlink MR
Page12
HW II Power Control
Measurement report
Uplink
measurement
report
Downlink
measurement
report
Page13
HW II Power Control
Interpolation
Compensation (optional)
Prediction (optional)
Filter
Page14
HW II Power Control
Page15
HW II Power Control
MR
MR
MR
No. n+4
MR
MR
No. n
Missing by
some reasons
Page16
Data Configuration of MR
Preprocessing
Page17
HW II Power Control
MR. compensation
1. Put the current receiving measurement report into the measurement report
compensation queue.
2. Record the changed information of the transmitting power according to the
MS and BTS power levels in the measurement report.
3. After finish the measurement report interpolation, system will compensate
the receiving level of the history measurement report according to the power
change information. The compensated measurement reports will be the
original data in the filter process.
4. Filter the compensated measurement reports.
Page18
Page19
HW II Power Control
MR. prediction
Implementation procedure
1. Analyze the tendency of MR by the historical measurement
Page20
Page21
HW II Power Control
MR
MR
MR
MR
MR
MR
Filter----Average several
consecutive MRs
Page23
Page24
Page26
Page27
AdjStep_Lev
AdjStep_Qul
max(AdjStep_Lev,AdjStep_Qul)
AdjStep_Lev
AdjStep_Qul
No action
AdjStep_Lev
No action
AdjStep_Lev
AdjStep_Lev
AdjStep_Qul
AdjStep_Lev
AdjStep_Lev
AdjStep_Qul
AdjStep_Lev
No action
AdjStep_Lev
No action
AdjStep_Qul
AdjStep_A
No action
AdjStep_Qul
AdjStep_B
No action
No action
No action
max(AdjStep_Lev,AdjStep_Qul)
Page28
Page30
Power control will not execute if the signal level and quality
is within the threshold bands.
Page31
Page32
Page35
Page38
Exercise
Given conditions:
The uplink receiving level is -55dBm, the quality is level 0. Power control algorithm is
HW II.
Data configuration is as follows: Uplink signal level upper threshold: -60dBm, uplink
signal level lower threshold: - 80dBm. Uplink signal upper quality threshold: level 1.
Uplink signal lower quality threshold: level 2. The downward adjustable step size of
quality band 0 is 16dB, of quality band 1 is 8dB, and of quality 2 is 4 dB. The upward
adjustable step size of receiving level is 16dB. The upward or downward adjustable
step size for power control by quality are both 4dB.
Question: What will be the uplink stable receiving level after power control?
Page39
Exercise
Answer.
Page40
Exercise
Answer .
Page41
Content
1. Power Control Overview
Page42
Contents
3. HW III Power Control Algorithm
3.1 HW III Power Control Algorithm
3.2 HW III Power Control Optimization Algorithm
Page43
YES
Is active PC allow?
The number of
MRs[SdMrCutNum/
TchMrCutNum]?
NO
YES
YES
NO
YES
New transmit
power=current
one+[MAXUpStep]
YES
Interpolated MRs
MR.
Preproces
-sing
End
NO
NO
Is PC allowed?
YES
NO
NO
Exponential filtering
Adjust transmit power
PC interval >
[PwrCtrlAdjPeriod]
NO
End
YES
NO
Implement PC
YES
Page44
End
Interpolation method
Filter calculation
Page45
Page46
Page47
Quality filter
Quality Class
CIR (dB)
22
18
16
14
12
Page48
Exponent filter
ca_filtered1 (1)=ca(1)
k=1
k>1
Page49
Filter algorithm
k=1
1<k<w
Page50
k>=w
Page51
10
ca _ filtered( k )
10
Rx_lev
10
c(k )
10
10
Useful signel
I (k )
10
(1)
Interference
(2)
(3)
Page53
qa _ filtered ( k )
10
Input c(k) to (3), get g(k) = p(k) c(k). So calculate the g(k)
Page54
Page55
Page56
Page57
Adjustment protection
Page61
Page62
Page63
Question
Given condition
ULRexLevHighThred30
ULRexLevLowThred20
ULFSRexQualHighThred20
ULFSRexQualLowThred16
ULRexLevAdjustFactor4 ULRexQualAdjustFactor6
ULMAXDownStep8 ULMAXUpStep8
Quality Class
CIR (dB)
22
18
16
14
12
Page64
Question
Answer:
step(k) = - ( sfactor( BsTxMaxPower - g(k) - SThr)
qfactor( qa_filtered(k) - QThr) )
30 20
20 16
{{0.4 [33 110 (
110)]} 0.6 (16
)}
2
2
2dB
After power control
Power output of MS: 33-2=31dBm
Suppose the current g(k)=115dB, current quality:2(CIR=16dB)then
For level-90dBm<31-115<-80dBm
Page65
Contents
3. HW III Power Control Algorithm
3.1 HW III Power Control Algorithm
3.2 HW III Power Control Optimization Algorithm
Page66
Page67
Page68
transmit power.
Page69
Dual-coefficient Filter
A = (1.012*L-0.7505)/(L+1.848)
B: [DLRexLevExponentFilterLen], [DLRexQualExponentFilterLen],
[ULRexLevExponentFilterLen], [ULRexQualExponentFilterLen]
Page70
That is:ca_comp (k) has higher weight than ca_filtered (k-1) , then the result
ca_filtered (k) is lower RxLev.
-60dBm
S
-75dBm
-75dBm
Expected Power
S<S fast
increasing
-78dBm
-80dBm
-78dBm
Expected Power
Page71
That is:ca_comp (k) has smaller weight than ca_filtered (k-1) , then the result
ca_filtered (k) is lower RxLev.
-60dBm
Expected Power
S
-75dBm
-78dBm
-75dBm
-78dBm
-80dBm
Expected Power
Page72
Dual-coefficient Filtering--Data
Configuration
Page73
HW PC III optimization algorithm adopts two sets of factors, and it can help the
system to avoid too low transmit power.
Page75
Page76
Content
1. Power Control Overview
Page78
Contents
4. Other Algorithms
4.1 SAIC Power Control
Page79
Introduction to SAIC
Page80
Page81
Page82
Summary
Page84
Thank you
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