Unit 4

Assembly Language Programming

Introduction
Machine Language Programming
One way to write a program is to assign a fixed binary
pattern for each instruction and represent the program by
sequencing these binary patterns.
Such a program is called a Machine language program
or an object program

Eg:
0011
0000
0000
0000
1000
0011
0110
0000
0110

1110
0101
0110
0110
0000
1010
0100
0000
0110

; LOAD A Register with

; Value 5
; LOAD B Register with
; Value 10
; A <- A + B
; store the result
; into the memory location
; whose address is 100
; halt processing

Assembly Language Programming

Use of symbols in programming to improve the

readability.
Giving symbolic names for each instruction.
These names are called mnemonics and a
program written using these symbols are called
as Assembly Language Program.

Eg:

LOAD A, 5
LOAD B, 10
ADD A, B
LOAD (100), A

HALT

;
;
;
;

load A reg with 5

load B reg with 10
A=A+B
save the result in
location 100
; halt processing

Features of ALP

For using Assembly language, the

programmer needs to know the internal
Architecture of the Microprocessor.
The Assembly language written for one
processor will not usually run on other
processors.
An assembly language program cannot be
executed by a machine directly, as it not in
a binary form.

An Assembler is needed in order to

translate an assembly language (source
pgm) into the object code executable by
the machine.

Unlike the other programming languages,

assembly language is not a single
language, but rather a group of
languages.

Each processor family (and sometimes

individual processors within a processor
family) has its own assembly language.

Comparison of Assembly language with High

level languages

Assembly languages are close to a one to one

correspondence between symbolic instructions and
executable machine codes.

Assembly languages also include directives to the

assembler, directives to the linker, directives for
organizing data space, and macros.

Assembly language is much harder to program than

high level languages. The programmer must pay
attention to far more detail and must have an intimate
knowledge of the processor in use.

High level languages are abstract. Typically a

single high level instruction is translated into
several (sometimes dozens or in rare cases
even hundreds) executable machine
language instructions.

Modern object oriented programming

languages are highly abstract

But high quality assembly language programs can

run much faster and use much less memory and
other resources than a similar program written in a
high level language.

Speed increases of 2 to 20 times faster are fairly

common, and increases of hundreds of times faster
are occasionally possible.

Assembly language programming also gives direct

access to key machine features essential for
implementing certain kinds of low level routines, such
as an operating system kernel or microkernel, device
drivers, and machine control.

High level programming languages are much easier

for less skilled programmers to work in and for semitechnical managers to supervise.

High level languages allow faster development times

than work in assembly language, even with highly
skilled programmers.

Development time increases of 10 to 100 times

faster are fairly common.

Programs written in high level languages (especially

object oriented programming languages) are much
easier and less expensive to maintain than similar
programs written in assembly language (and for a
successful software project, the vast majority of the
work and expense is in maintenance, not initial
development).

Advantages:1.

Performance: An expert Assembly language

programmer can often produce code that is much
smaller and much faster than a high level language
programmer can. For some applications speed and
size are critical. Eg:- code on a smart card, code in a
cellular telephone, device drivers, BIOS routines etc.

2. Access to the Machine: Procedures can have

complete access to the Hardware (Not possible in High
level language)
eg: low level interrupt and trap handlers in OS

Format of Assembly program

LABEL OPCODE OPERAND COMMENTS

1. Labels :Begins from column1. Should

start with a letter. After the letter a
combination of letters and numbers
may be used. Restricted by most
assemblers from 6 to 8 characters. Use
is to identify opcodes and operands.
Are needed on executable statements,
so that the statement can be branched
to.

2. Opcode: Symbolic abbreviations for

operation codes or comment to the
Assembler. Specifies how data are to be
manipulated, which is residing within a
microprocessor register or in the main
memory. Eg: MOV, LD, ADD
3. Operand: use to specify the addresses or
registers used by the operands by the
Machine instructions. Operands may be
Registers, memory location, constants etc.
4. Comments: prefixed by ; for
documentation

Eg
LABEL OPCODE OPERAND COMMENTS

NEXT: ADD AL,07H ; ADD 07H to AL register

8086 CPU ARCHITECTURE

16 bit processor

The microprocessors functions as the CPU in the stored

program model of the digital computer.
Its job is to generate all system timing signals and
synchronize the transfer of data between memory, I/O,
and itself
The microprocessor also has a S/W function.
It must recognize, decode, and execute program
instructions fetched from the memory unit.
This requires an Arithmetic-Logic Unit (ALU) within the
CPU to perform arithmetic and logical (AND, OR, NOT,
compare, etc) functions .

8086 is Intels first 16-bit microprocessor designed in

1978
Here the 16 bit means that its ALU, its internal
registers, and most of its instructions r designed to
work with 16-bit binary words.
8086 has a 16 bit data bus , so it can read data from
or write data to memory either 16 bits or 8 bits at a
time.
8086 has a 20-bit address bus, can access up to
1MB(2 20) ie, 1,048,576 memory locations.
16 bit word will b stored in 2 consecutive memory
locations.
Packaged in a 40 pin Integrated Circuit

8086 Internal Architecture

Divided into 2 functional units

BIU(Bus Interface Unit) and

EU(Execution Unit)
BIU fetches instructions, reads data from
memory and I/O ports and writes data to
memory I/O ports. It handles all transfers of
data and addresses on the buses for the
Execution Unit(EU).
Execution Unit(EU) executes instructions
that have already been fetched by the BIU;
tells BIU where to fetch instructions or data
from, decodes and executes instructions.

BIU and EU function independently

BIU interfaces 8086 to outside world
BIU provides all external bus operations
BIU contains segment registers, instruction
pointer, instruction queue and address
generation/bus control circuitry to provide
functions such as fetching and queuing of
instructions and bus control

BIUs instruction queue is FIFO (First In First

Out) group of Registers in which up to 6 bytes
of instruction code are pre fetched from
memory ahead of time. This is called as
pipelining
This is done in order to speed up program
execution by overlapping instruction fetch with
execution.
BIU has four 16-bit Segment Registers
Code Segment(CS), Data Segment(DS), Stack
Segment(SS) and the Extra Segment(ES)
Register

Register Structure

8086 has thirteen 16 bit registers and 9 flags.

SP:All PUSH and POP operations derive their address from

SP.
It points to the current top of the stack.
BP: within one stack there may b several data areas.
This register can b used to hold the offset of the base of a
data area in the current stack segment.
SI & DI :there r certain string operations provided by 8086.
Eg: MOV a string of bytes or word from one area to another.
SI and DI r used implicitly, in such instructions.
Eg:A string move instruction MOVS, SI points to the source
string byte to b moved and DI points to the corresponding
destination byte.

IP Instruction Pointer is a 16 bit register

and points to the next instruction to be
executed within the current code segment.
It is automatically updated by the 8086 as
program execution proceeds.
Flag register in the EU holds the status flags
typically after an ALU operation.

Flag Register

Carry Flay- set carry out of MSB

Parity Flag-set if res. has even
Auxiliary carry for BCD
Zero flag-set if res. is 0
Sign Flag=MSB of res
TrapFlag
Interrupt Enable Flag
String Direction Flag
Overflow Flag

All Registers

Segment Registers
CS,SS, DS,ES

Within the 1 MB of memory space the 8086 defines

four 64K-byte memory blocks called the code
segment, stack segment, data segment, and
extra segment.
Each of these blocks of memory is used differently by
the processor.
The code segment holds the program instruction
codes.
The data segment stores data for the program.
The extra segment is an extra data segment (often
used for shared data).
The stack segment is used to store interrupt and
subroutine return addresses.

Memory Segmentation in 8086

00500

Code Segment

0050

CS

0070

DS

Stack Segment

0090

SS

Extra Segment

0099

ES

006FF
00700

Data Segment

007FF

Unused Area
00900
0098F
00990
00A00

The four segment registers (CS, DS, ES, and SS) are
used to "point" at location 0 (the base address) of
each segment.
This is a little "tricky" because the segment registers
are only 16 bits wide, but the memory address is 20
bits wide.
The BIU takes care of this problem by appending four
0's to the low-order bits of the segment register.
In effect, this multiplies the segment register contents
by 16.

Address Formation

How the 20-bit address is formed?

Assume that the IP contains 0080H.
This means that the next instruction byte is located at
address 0080H within the current code segment.
The 20 bit adrs of this instruction is formed as
follows:
CS*16+IP=00500+0080=00580H.
Thus the actual adrs of the instruction is transformed
to the 20-bit addresses using an appropriate segment
register.
This adrs transformation is known as relocation.
As the segment registers r used for relocation of
adrses, they r also called segment relocation
registers.

Addressing Modes
The way in which an operand is specified is
called the Addressing Mode.
The 8086 processor supports:
Register AM
Immediate
Direct
Indirect mode through Base registers
Indirect mode through Index registers
Indirect mode through Sum of Base and
Index Registers

Relative mode through Base Register

Relative mode through Index Register
Relative mode through Base and Index
Register.
Implied Addressing mode

1.Register Addressing mode

Simplest of all addressing modes
Specifies the source operand,
destination operand or both to be
contained in an 8086 register.
Transfers a copy of a byte or word
from source register to destination
register
eg:- MOV AX, BX
ADD AX, BX

2.Immediate Addressing mode

Transfers immediate byte or word of

data into the destination Register
E.g.: MOV AX, 0FAH
ADD BX, 4

3.Direct Addressing mode

Address of the operand is directly
specified in the instruction itself.
Moves a byte or word between a
memory location and a register
E.g.: MOV [1234H], AX
Suppose DS contains 1000H
EA is DS X 10H + 1234H = 10000H +
1234H
= 11234H

4.Indirect Mode through Base Registers

Memory location is specified by Base

Registers.
E.g.: MOV [BX], CX

5.Indirect Mode through Index Registers

Memory location is specified by Index

Registers
E.g.: MOV [SI], CX

6.Indirect Mode through

Sum of Base and Index Registers

Memory location specified by sum of

Base and index Registers
E.g.: MOV [BX+SI], CX

7.Relative mode through Base Register

Memory location addressed by Base

register plus a displacement
E.g.: MOV [BX+4], CX

8.Relative mode through Index Register

Memory location addressed by Index

register plus a displacement
E.g.: MOV [SI+4], CX

9.Relative mode through Base and Index

Register

Memory location addressed by Base

and index register plus a displacement
E.g.: MOV ARRAY[BX+SI],DX

10.Implied Addressing mode

Instructions using this mode have no

operands.
E.g.: CLC ; clears the carry flag to zero

8086 Instruction Set

Can
1.
2.
3.
4.
5.
6.

b classified as shown:
Data Transfer Instructions
Arithmetic Instructions
Bit Manipulation Instructions
String Instructions
Program Execution Transfer Instructions.
Processor Control Instructions.

1.Data-transfer Instructions
A. General purpose byte or word instructions

MOV: copy byte or word from specified

source to destn. MOV AX, BX
PUSH: copy specified word to top of the
stack. PUSH BX
POP: copy word from TOS to specified
location. POP CX
PUSHA/POPA: copy all registers to stack
and copy words from stack to all regs.
XCHG: Exchange byte or word.
XCHG DX, AX

B. Simple I/O port transfer instructions

IN :copy a byte or word from specified byte

to accumulator. IN AL, 028h
OUT :copy a byte or word from accumulator
to specified port. OUT 028h,AL

C. Special Address transfer Instructions

LEA: Load Effective Address of operand to

specified register. LEA BX, START.
LDS: Load DS register and other specified
register from memory.
LES: Load ES register and other specified
register from memory.

D.Flag transfer instructions

LAHF: Load (Copy to) AH with the low byte

of the flag register.
SAHF: Store (copy) AH register to low byte
of flag register.
PUSHF: copy flag register to TOS
POPF: copy word at TOS to flag register.

2.Arithmetic Instructions
A. Addition Instructions

ADD: Add specified byte to byte or

specified word to word. ADD AX, BX
ADC: add byte+ byte+ carry flag or word+
word+ carry flag .
INC: increment specified byte or specified
word by 1.INC AX
AAA: ASCII Adjust after Addition
DAA: Decimal (BCD) adjust after addition

B. Subtraction Instructions

SUB :subtract byte from byte or word from word.

SUB AX, BX
SBB: Subtract byte and carry flag from byte or word
and carry flag from word.
DEC: Decrement the specified byte or specified word
by 1.
NEG: Negate-invert each bit of a specified byte or
word and add 1(2s complement).
CMP: compare 2 specified bytes or 2 specified words.
AAS: ASCII Adjust after Subtraction.
DAS: Decimal (BCD) adjust after subtraction

C. Multiplication instructions

MUL: Multiply unsigned byte by byte or

unsigned word by word.
IMUL: Multiply signed
AAM: ASCII Adjust after multiplication

D. Division Instructions

DIV: Divide unsigned word by byte or

unsigned double word by word
IDIV: Divide Signed
AAD: ASCII Adjust before division.
CBW: Fill upper byte of word with copies of
sign bit of lower byte.
CWD: fill upper word of double word with
sign bit of lower word.

3. Bit Manipulation Instructions

A. Logical Instructions

NOT: Invert each bit of a byte or word

AND :AND each bit in a byte or word with the
corresponding bit in another byte or word.
OR: OR
XOR: XOR
TEST: AND operands to update flags , but
dont change operands.

B. Shift Instructions

SHL/SAL: Shift bits of word or byte left, put

Zeros in LSB
SHR: Shift bits of word or byte right, put 0s
in MSBs.
SAR: Shift bits of word or byte right , copy
old MSB into new MSB.

C. Rotate Instructions

ROL: Rotate bits of byte or word left, MSB to

LSB and to CF.
ROR: Rotate bits of byte or word right, LSB
to MSB and CF.
RCL: Rotate bits of byte or word left, MSB to
CF and CF to LSB.
RCR: Rotate bits of byte or word right, LSB
to CF and CF to MSB.

4. String Instructions

A String is a series of bytes or a series of

words in sequential memory locations.
A String often consists of ASCII character
codes.
B- used to indicate that a string of bytes is
to b acted upon.
W- used to indicate that a string of words
is to b acted upon

REP: An instruction prefix. Repeat following

instruction until CX=0.
REPE/REPZ: Repeat instruction until CX=0 or
ZF<>1.
REPNE/REPNZ: Repeat instruction until CX=0
or ZF=1.
MOVS/MOVSB/MOVSW: move byte or word
from 1string to another
COMPS/COMPSB/COMPSW: compare 2
strings byte/word
INS/INSB/INSW: input string byte or word
from port.

OUTS/OUTSB/OUTSW: output string

byte/word to port
SCAS/SCASB/SCASW: scan a string ,
compare a string byte with a byte in AL or a
string word with a word in AX.
LODS/LODSB/LODSW: load string byte into
AL or string word into AX.
STOS/STOSB/STOSW: store byte from AL
or word from AX into string

4. Program Execution transfer instructions

A. Unconditional transfer

CALL: call a procedure (sub program),

save return address on stack
RET: return from procedure to calling
program
JMP: go to specified address to get
next instruction

B. Conditional transfer

JA/JNBE: jump on above or jump

on not below or equal
JC: jump on carry
JE/JZ: jump on equal or zero.
JO: jump on overflowetc

C. Iteration control instructions

LOOP: Loop through a series of instructions

until CX=0.
LOOPE/LOOPZ : Loop thru a seq. of
instructions while ZF=1 and CX<>0.
LOOPNE/LOOPNZ : Loop thru a seq. of
instructions while ZF=0 and CX<>0.
JCXZ: jump to specified adrs if CX=0

D. Interrupt instructions

INT: Interrupt pgm execution, call

service procedure.
INTO: Interrupt pgm execution if OF=1.
IRET: Return from interrupt service
procedure to main program.

6.Processor Control Instructions

A. Flag set/clear Instructions

STC: set CF to 1
CLC: clear CF to 0.
CMC: complement CF
STD: set Direction Flag DF to 1(decrement
string pointers)
CLD: clear DF to 0.
STI: set Interrupt enable flag to 1(enable
INTR interrupt).
CLI: clear interrupt enable flag to 0 (disbale
INTR interrupt)

B. External Hardware synchronization instructions

HLT: Halt (do nothing) until interrupt or reset.

WAIT: wait ( do nothing) until signal on the
TEST pin is low.
ESC: escape to external coprocessor such as
8087 or 8089
LOCK: an instruction prefix. Prevents another
processor from taking the bus while adjacent
instruction executes.

C. No operation instructions

NOP: no action except fetch and

decode.

8086 Pin out Diagram

Min/Max mode operation

Minimum mode operation

Minimum mode is one of the two different hardware

modes of the Intel 8086 processor.
Mode selection is accomplished by how the chip is
hard-wired in the circuit.
Specifically, pin #33 (MN/MX) is used to select the
mode.
If it is wired to voltage (+5V) ,it is in MIN mode.
Changing the state of pin #33 changes the function
of certain other pins.
Mode cannot be changed by software.
The minimum mode of operation is for small
systems.
The 8086 is operated in MIN mode in systems such
as SDK-86(System Design Kit) where it is the only
microprocessor on the system bus

The pins that are available exclusively in the

minimum mode are (bold indicates active low )
24-Interrupt Acknowledge INTA- is a response
to the INTR pin.
25-Address Latch Enable ALE -indicates the
8086 adrs/data bus contains adrs infrmn.
26-Data Enable - DEN external data bus buffers
27-Data Transmit/Receive - DT/R-shows
processors data bus is txing or rxing.
28-Status Line - M/IO-selects memory or I/O
29-Write WR- indicates that the 8086 is
outputting data to memory or I/O devices.
30-Hold Acknowledge HLDA-indicates the
processor entered in a HOLD state
31-Hold HOLD-it requests a DMA.

Maximum mode operation

MAXIMUM mode is for large applications

such as multiprocessing.
For MAX mode pin 33 should b wired to
ground .
When MN/MX is connected to ground the
8086 treats pin 24-33 in MAX mode.

The pins that are available exclusively in the

maximum mode are

24,25-QS1, QS0-Que Status -shows the

status of the internal instruction queue.
26,27,28-s0,s1,s2-the status pins indicates
the function of the current bus cycle. This
signals r normally decoded by the 8288 bus
controller.
29-LOCK-is used to lock peripherals of the
system.
30,31-RQ/GT1,RQ/GT0-Request/Grant pin
request DMA during max. mode operation.

INTEL 80386 a 32 bit processor

Intels 32-bit processor

Provides memory management,
multitasking support, pipelined
architecture, address translation caches,
and a high-speed bus interface in a single
chip
8 general purpose 32-bit registers
Processor can handle 8-bit, 16-bit and 32-bit
data types (operands)
Can access up to 4 GB of main memory
Separate 32-bit data and address pins and
generate a 32-bit physical address

Highly pipelined, can perform instruction

fetching, decoding, execution, and memory
management functions in parallel
On-chip memory management and protection
hardware translates logical addresses to
physical addresses
Supports virtual memory, paging

Internal architecture of 80386

Execution unit
Control
Unit

Segment unit
Segment
Register

Page unit
TLB

Page translator
Data Unit

Segment
translators

Protection
Test Unit

decoder
Instruction
queue

Decode unit

Prefetch
queue
prefetcher

Prefetch unit

biu

Internal Architecture
Includes 6 functional units that operate in parallel
1. Bus interface unit:
Interfaces between the 80386 with memory and I/O.
Based on internal requests for fetching instructions and
transferring data from the code prefetch unit, the
80386 generates the address, data, and control signals
for the current bus cycles.

2.Code prefetch unit:

Prefetches instructions when the BIU is not
executing bus cycles.
It then stores them in a 16-byte instruction queue
for execution by the instruction decode unit.
3.Instruction decode unit:
Translates instructions from the prefetch unit queue
into microcodes.
The decoded instructions are then stored in an
instruction queue (FIFO) for processing by the
execution unit.

4. Execution unit:
Processes the instructions from the instruction queue.
It contains a control unit, a data unit and a protection
test unit.
Control unit contains microcode and parallel hardware
for fast multiply, divide and EA calculation.
Data unit includes an ALU, 8 general-purpose
registers, and a 64-bit barrel shifter for performing
multiple bit shifts in one clock. It carries out data
operations requested by the control unit
Protection test unit checks for segmentation
violations under the control of the microcode

5.Segmentation unit:
Translates logical addresses into linear addresses at
the request of the execution unit
6.Paging unit.
Translated linear address is sent to the paging unit.
Upon enabling of the paging mechanism, the 80386
translates these linear addresses into physical
addresses.

80386 registers

General registers:
Segment registers:
Index and pointers:
Indicator:

EAX EBX ECX EDX

CS DS ES FS GS SS
ESI EDI EBP EIP ESP
EFLAGS

General registers

General registers are the mostly used. They all can

be broken down into 16 and 8 bit registers.
32 bits: EAX EBX ECX EDX
16 bits: AX BX CX DX
8 bits: AH AL ,BH BL, CH CL, DH DL
EAX, AX, AH, AL: Accumulator register. It is used
for I/O port access, arithmetic, etc.
EBX, BX, BH, BL: Base register. It is used as a
base pointer for memory access.
ECX, CX, CH, CL: Counter register. It is used as a
loop counter and for shifts.
EDX, DX, DH, DL: Data register. It is used for I/O
port access, arithmetic, some interrupt calls.

Segment registers
Segment registers hold the segment address of
various items.
They are only available in 16 bit values. Some of
them are critical for the good execution of the
program:
CS: Holds the Code segment in which your
program runs. Changing its value might make the
computer hang.
DS: Holds the Data segment that your program
accesses. Changing its value might give erroneous
data.
ES, FS, GS: These are extra segment registers
available for far pointer addressing like video
memory.
SS: Holds the Stack segment your program uses.
Sometimes has the same value as DS. Changing its
value can give unpredictable results, mostly data
related.

Indexes and pointers

Indexes and pointers are the offset part of an
address.
They have various uses but each register has a
specific function.
They are some times used with a segment register to
point to a far address (in a 1Mb range).
ES: EDI DI: Destination index register Used for
string, memory array copying and setting and
for far pointer addressing with ES
DS: ESI SI: Source index register Used for string
and memory array copying
SS: EBP BP: Stack Base pointer register
Holds the base address of the stack
SS: ESP SP: Stack pointer register . Holds the top
address of the stack
CS: EIP IP: Index Pointer. Holds the offset of the
next instruction .It can only be read

The EFLAGS register

The EFLAGS register hold the state of the
processor.
It is modified by many instructions and is
used for comparing some parameters,
conditional loops and conditional jumps.
Each bit holds the state of specific parameter
of the last instruction.

80386 Addressing modes

80386 provides 11 addressing modes:
Register Operand Mode : Instructions
operate on register operands. These
registers can be 8-bit, 16-bit or 32-bit
registers
E.g.: MOV EAX, EBX
DEC ECX (decrements ECX by 1)
Immediate Operand Mode : Immediate
operand is given in the instruction itself
E.g.: MOV EDX,5167810FH

In the remaining modes, the operand is

located in a memory segment. Memory
operand address in these modes is
calculated using segment selector and offset
values
Direct Mode : The operands effective
address is included as part of the instruction
as 8, 16, or 32 bit displacement
E.g.: MOV [12567H], EAX
Register Indirect Mode : The offset is
stored either in any of the general purpose
registers or in ESI, EDI, EBX
E.g.: MOV [EBX], ECX

Based Mode : The contents of a Base register

are added to a displacement to obtain the
operands effective address
E.g.: MOV [EDX+16], EBX
Indexed Mode : The contents of an Index
register are added to a displacement to obtain
the operands effective address
E.g.: MOV [ESI+4], EBX
Based Indexed Mode : The operand is stored
at a location whose address is calculated by
adding the contents of any of the base registers
with the contents of index registers
E.g.: MOV [ESI+EDX], EBX

Based Indexed Mode with Displacement :

In this mode the offset of the operand is
calculated by adding an 8-bit or 16-bit or 32-bit
immediate displacement with the contents of a
base register and an index register
E.g.: MOV [EBX] [EBP+0F247822AH], ECX

Scaled Indexed Mode : Contents of an Index

register are multiplied by a scale factor that
may be added to a displacement to obtain the
operands effective address. Valid scale factors
are 1,2,4 and 8
E.g.: MOV START[EBX * 8], ECX

Based Scaled Indexed Mode : Contents of

an index register are multiplied by a scale
factor and then added to Base register
E.g.: MOV [EBX + 2 * ESI], AX

Based Scaled Indexed Mode with

displacement: contents of index register are
multiplied by scale factor and the result is
added to base register and displacement
E.g.: MOV [ESI * 8][EBP + 60H], ECX

Pseudo instructions (Assembler Directives)

Pseudo instructions are instructions entered into the

source code along with the assembly language.
They do not get translated into object code but are
used as special instructions to the assembler to
perform some special functions.
The assembler will recognize pseudo instructions that
assign memory space, assign addresses to labels,
format the pages of the source code and so on.
They are usually placed in the op-code field. If any
labels or data are required by the pseudo instruction,
they are placed in the label or operand field as
necessary.

Some common pseudo instructions are:

1.

ORG-ORIGIN: This is used, when it is necessary to

place the program in a particular location in memory.
As the assembler is translating the source code, it
keeps an internal counter that keeps track of the
address for the machine code.
Eg: ORG 2000H-tells the assembler to set the
location counter to 2000H

2.

ASSUME: is used to tell the assembler the name of

the logical segment it should use for a specified
segment.
Eg: ASSUME CS:CODE tells the assembler that the
instructions for a program are in a logical segment
named CODE.
in instruction MOV AX,[BX], after it reads ASSUME
DS: DATA, it will know that the memory location
referred to by [BX] is in the logical segment DATA.

3. EQU-EQUATE : The EQU instruction is used to assign the data

value or address in the operand field to the label in the label field.
eg:- TEN EQU 10
NINE EQU 9
ORG 1000
MOVE AL,TEN
ADD AL,NINE
4. DB-Define Byte: is used to declare a byte-type variable.
Eg: Temp DB 42H- tells the assembler to reserve 1 byte of memory
for a variable named Temp and to put the value 42H in that
memory location when the program is loaded into RAM to be run.
5. DW-Define Word: FIRSTNO DW 437AH
STORAGE DW 100 DUP(0)-reserve an array of 100
words of memory and initialize all 100 words with 0000.
STORAGE DW 100 DUP(?)- reserve an array of 100
words of memory but leave the word uninitialized.

6.END-is put after the last statement of a

program to tell the assembler that this is the
end of the program module. The assembler
will ignore any statement after an END
directive.

MASM: The Microsoft Macro Assembler

The Microsoft Macro Assembler (abbreviated

MASM) is an assembler for the X86 family of
microprocessors.
It was originally produced by Microsoft for
development work on their MS-DOS, and was
for some time the most popular assembler
available for that operating system.
It supported a wide variety of macro facilities
and structured programming idioms, including
high-level constructions for looping, procedure
calls and alternation (therefore, MASM is an
example of a high-level Assembler).

Later versions added the capability of

producing programs for the Windows operating
systems that were released to follow on from
MS-DOS.
MASM is one of the few Microsoft development
tools for which there was no separate 16-bit
and 32-bit versions

MACROS

If we need to use a group of instructions

several times throughout a program,
there are 2 ways which avoid having to
write the group of instructions each time
we want to use it.
Use

separate procedure
Use Macro

When the repeated group of instructions is too

short or not appropriate to be written as a
procedure , we use macro.
A MACRO is a group of instructions we bracket
and give a name to the start of the our
program.
Each time we call the macro in our program,
the assembler will insert the defined group of
instructions in place of the call.
Ie, The assembler generates machine codes for
the group of instructions each time the macro
is called.

Replacing the macro with the instructions it

represents is called macro expansion.
Here the generated codes are right in-line
with the rest of the program.
Therefore, using macro avoids the overhead
time involved in calling and returning from a
procedure.
One drawback of macro is each time generating
in-line code causes more memory consumption.

Mainly 3 parts:
MACRO header (MACRO)
Text or Body
Pseudoinstructions marking the end of
the instruction (e.g.:- ENDM)

e.g.:-Without Macros

MOV
MOV
MOV
MOV

EAX, P
EBX, Q
Q, EAX
P, EBX

MOV
MOV
MOV
MOV

EAX, P
EBX, Q
Q, EAX
P, EBX

With Macros

SWAP MACRO
MOV EAX, P
MOV EBX, Q
MOV Q, EAX
MOV P, EBX
ENDM
SWAP
SWAP

When an assembler encounters a macro

definition, it saves it in a Macro definition
Table for subsequent use.
From that point, whenever the name of macro
appears on opcode, the assembler replaces it
by the macro body.
The use of a macro name as an opcode is
called a macro call and replacement by macro
body is called macro expansion
Macro expansion occurs during the Assembly
process and not during execution of the
program.

Macros with parameters

Without Macros
MOV
MOV
MOV
MOV

EAX, P
EBX, Q
Q, EAX
P, EBX

MOV
MOV
MOV
MOV

EAX, P
EBX, Q
Q, EAX
P, EBX

With Macros
CHANGE MACRO P1, P2
MOV EAX, P1
MOV EBX, P2
MOV P2, EAX
MOV P1, EBX
ENDM
CHANGE P, Q
CHANGE R, S