003-HCS12 Instruction Set

HCS12
Instruction set
HCS12 Technical Training

Module 3 - Instruction Set, Slide 1
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.
INSTRUCTION SET
Data Handling
Arithmetic
Logic
Data Test
Branch
Jump & Subroutine Calls

DATA HANDLING INSTRUCTIONS

(DATA MOVEMENT)
FUNCTION
MNEMONIC
LOAD ACMLTR
LDAA
LDAB
(M)
(M)
LDD
LDX
LDY
LDS
(M)
(M+1)
LOAD 16 BIT REG
LOAD <EA>
OPERATION
A
B
RH
RL
LEAX
<ea>
LEAY
<ea>
LEAS
<ea>
SP
Y
2000
MEM
ACCB
EXAMPLE: LEAX B,Y
B
X REG
25
2025


(DATA MOVEMENT)
FUNCTION
STORE ACMLTR
STAA
STAB
STORE 16 BIT REG
STD
STX
STY
STS
PUSH DATA
TO STACK
PSHA
PSHB
PSHC
PSHD
PSHX
PSHY
PULA
PULB
PULC
PULD
PULX
PULY
PULL DATA
FROM STACK
MOVE
EXAMPLE:
OPERATION
MNEMONIC
MOV
MOVW
A
B
(M)
(M)
RH
RL
(SP) - 1
( REG)
(M)
(M+1)
SP
M(SP)
(SP) - 2
SP
(RH : RL ) (M(SP) ):(M(SP+1) )
(M(SP) )
REG
(SP) + 1
SP
(M(SP)):(M (SP)+1 )
(SP) + 2
MEM
RH: R L
SP
MEM
2,X+ , 2,-Y
STACK OPERATION
EXAMPLE:
PSHX
PSHX
BEFORE
AFTER
B7
MEM
B7
B0
MEM
B0
INCREASING
ADDRESSES
SP
$4000
TOP OF STACK
INCREASING
ADDRESSES
SP
SP
SP
$3FFE
$3FFF
$4000
XH
XL
TOP OF STACK


(TRANSFER AND EXCHANGE)
FUNCTION
MNEMONIC
OPERATION
TRANSFER DATA
TBA
TAB
B
A
TXS
TYS
SP
TSY
TSX
SP
TRANSFER REG TO REG
TFR
EXCHANGE
EXG
EXCHANGE DATA
XGDX
XGDY
A
B
A, B, CCR, D, X, Y, SP
D
D
X
Y
EXAMPLE1: TFR X ,A
EXAMPLE2: EXG Y ,B


(ALTER DATA)
FUNCTION
MNEMONIC
OPERATION
DECREMENT
DEC
DECA
DECB
(M)-1
A-1
B-1
DEX
DEY
DES
X-1
Y-1
S-1
INC
INCA
INCB
(M)+1
A+1
B+1
(M)
A
B
INX
INY
INS
X+1
Y+1
S+1
X
Y
S
INCREMENT
(M)
A
B
X
Y
S


(ALTER DATA)
FUNCTION
MNEMONIC
OPERATION
COMPLEMENT, 2'S
(NEGATE)
NEG
NEGA
NEGB
0-(M)
0-A
0-B
COMPLEMENT, 1'S
COM
COMA
COMB
(M)
A
B
CLEAR
CLR
CLRA
CLRB
0
0
0
BIT(S) CLEAR
BCLR
(M)
MASK
(M)
BIT(S) SET
BSET
(M) + MASK
(M)
(M)
A
B
(M)
A
B
(M)
A
B
Bit Manipulation Example: BSET OFFSET,X, #MASK


FUNCTION
MNEMONIC
MININUM OF TWO
UNSIGNED 8-BIT
VALUE
MININUM OF TWO
UNSIGNED 8-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
LOOP
MINA
BHS
OPERATION
MINA
MIN ((A), (M))
(A)
MINM
MIN ((A), (M))
(M)
MAXA
MAX ((A), (M))
(A)
MAXM
MAX ((A), (M))
(M)
1,X+
LOOP


FUNCTION
MNEMONIC
MININUM OF TWO
UNSIGNED 16-BIT
VALUE
MININUM OF TWO
UNSIGNED 16-BIT
VALUE
EMINM
MAXIMUM OF TWO
UNSIGNED 16-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
EMIND
EMAXD
EMAXM
OPERATION
MIN ((D), (M:M+1))
(D)
MIN ((D), (M:M+1))

M:M+1
MAX ((D), (M:M+1))
(D)
MAX ((D), (M:M+1))

M:M+1


(SHIFT AND ROTATE)
FUNCTION
MNEMONIC
ROTATE LEFT
ROL
ROLA
ROLB
M
A
B
ROR
RORA
RORB
M
A
B
ASL(LSL)
ASLA(LSLA)
ASLB(LSLB)
ASLD(LSLD)
M
A
B
D
ROTATE RIGHT
SHIFT LEFT,
ARITHMETIC
(LOGICAL)
OPERATION
b7
b7
SHIFT RIGHT,
LOGICAL
ASR
ASRA
ASRB
M
A
B
LSR
LSRA
LSRB
LSRD
M
A
B
D
b0
0
b7
b0
A
SHIFT RIGHT,
ARITHMETIC
b0
b15
b0
b7
b0
0
b7
0
A
b15
b0
b0

DATA TEST INSTRUCTIONS
FUNCTION
MNEMONIC
TEST
BIT TEST
BITA
BITB
A (M)
B (M)
COMPARE
CBA
CMPA
CMPB
A-B
A-(M)
B-(M)
CPD
CPX
CPY
CPS
R L-(M+1)
R H-(M)-C
COMPARE STACK
TEST, ZERO OR
MINUS
TST
TSTA
TSTB
SP - ( M :M +1)
(M)-0
A-0
B-0

CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3)
*Use for signed

arithmetic only
MNEMONIC
CONDITION
CCR TEST
INDICATION
(L) BMI
MINUS
N=1
r=NEGATIVE
(L) BPL
PLUS
N=0
r=POSITIVE
*(L) BVS
OVERFLOW
V=1
r=SIGN ERROR
*(L) BVC
NO OVERFLOW
V=0
r=SIGN OK
*(L)BLT
LESS
[N V]=1
A<M
*(L)BGE
GREATER OR EQUAL
[N V]=0
A >= M
* (L)BLE
LESS OR EQUAL
[Z+(N V)]=1
A <= M
*(L) BGT
GREATER
[Z+(N V)]=0
A>M
(L)BEQ
EQUAL
Z=1
A=M
(L) BNE
NOT EQUAL
Z=0
A <> M
(L)BHI
HIGHER
[C+Z]=0
A>M
(L) BLS
LOWER OR SAME
[C+Z]=1
A <= M
(L)BCC (BHS)
CARRY CLEAR
C=0
A >= M
(L) BCS (BLO)
CARRY SET
C=1
A<M

Indication
refers to the
use of a
CMPA M
instruction
immediately
before the
branch
CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3)

FUNCTION
MNEMONIC
DECREMENT & BRANCH
DBEQ
DBNE
INCREMENT & BRANCH
IBEQ
IBNE
TEST & BRANCH
OPERATION
COUNTER - $01
COUNTER
IF COUNTER =0, THEN (PC)+$0003 +REL
PC
COUNTER - $01,
COUNTER
IF COUNTER <>0, THEN (PC)+$0003 +REL
PC
COUNTER + $01
COUNTER
IF COUNTER =0, THEN (PC)+$0003 +REL
COUNTER + $01
COUNTER
IF COUNTER <>0, THEN (PC)+$0003 +REL
PC
TBEQ
IF COUNTER = 0, THEN PC+$0003 + REL
PC
TBNE
IF COUNTER <>0, THEN PC+$0003 + REL
PC
EXAMPLE:
LOOP
PC
MOVW $1000, 2,X+

DBNE D,LOOP
BRANCH IF BITS SET OR CLEAR (3 of 3)

SINGLE INSTRUCTION TO LOGICALLY "AND" MASK WITH OPERAND AND
BRANCH IF BITS ARE EITHER SET OR CLEARED.
USEFUL FOR POLLING INTERRUPT STATUS FLAGS, AND FOR MAKING PROGRAM
DECISIONS BASED ON BIT(S) VALUES.
BRANCH IS TAKEN FROM NEXT INSTRUCTION ADDRESS (OCL+4, 5, OR 6 )
BRSET
BRCLR
OCL
(M) MASK SERVICE
OP CODE
OPERAND
MASK
BRANCH DISP.
ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX, IDX1 & IDX2.
EXAMPLE:
WAIT BRCLR PORTD,Y $80, WAIT
ARITHMETIC INSTRUCTIONS (4 of 4)
FRACTIONAL DIVIDE INSTRUCTION
FRACTIONAL DIVIDE
FDIV
RADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSB

IF NUMERATOR IS GREATER THAN OR EQUAL TO THE DENOMINATOR,
THEN V FLAG IS SET.
RESULT EXAMPLES:
A RESULT OF 1 IS 1/$10000 WHICH IS .0001
A RESULT OF $C000 IS $C000/$10000 WHICH IS .75
A RESULT OF $FFFF IS $FFFF/$10000 WHICH IS .9999

FUNCTION
MNEMONIC
OPERATION
ADDA
ADDB
ADDD
A + (M)
A
B + (M)
B
D L + (M+1)
DL; DH + M + C
ADD
ACCUMULATORS
ABA
ABX
ABY
A+B
X+B
Y+B
ADD WITH CARRY
ADCA
ADCB
A+M+C
B+M+C
DECIMAL ADJUST
DAA
ADD
DH
A
X
Y
A
B
CONVERTS BINARY ADDITION OF

BCD CHARS INTO BCD FORMAT

FUNCTION
MNEMONIC
OPERATION
SUBTRACT
SUBA
SUBB
SUBD
A (M)
B (M)
D L (M+1)
SUBTRACT
ACCUMULATORS
SBA
SUBTRACT WITH
CARRY
SBCA
SBCB
MULTIPLY
MUL
A B
A
B
DL; DH (M) C
A
A (M) C
B (M) C
A*B
A
B
EXTENDED MULTIPLY
EMUL
D*Y
Y:D
EXTENDED MULTIPLY
SIGNED
EMULS
D*Y
Y: D

DH
DIVIDE INSTRUCTIONS
OPERATION
D REG / X REG
RESULT
QUOTIENT IS IN X
REMAINDER IS IN D
INTEGER DIVIDE
IDIV/IDIVS
RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB

EXTENDED DIVIDE 32-BIT BY 16-BIT ( [UN ]SIGNED)
EDIV EXAMPLE:
OPERATION
EDIV/EDIVS
EDIV[ S ]
(Y:D)/ (X)
Y; REMAINDER
V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000

V = 1, IF RESULT > $7FFF FOR SIGNED, UNDEFINED IF DIVISOR IS $0000
C = 1, IF DIVISOR WAS $0000
EXTENDED MULTIPLY AND ACCUMULATE

(EMACS)
OPERATION:
(M (X) : M (X+1) ) * (M (Y) : M (Y+1) ) + M ~ M+3)
15
M ~ M+3
15
EXAMPLE:
EMACS
$2500
(* 32-BIT RESULT *)

LOGIC INSTRUCTIONS
FUNCTION
MNEMONIC
AND
ANDA
ANDB
ANDCC
A (M) A
B (M) B
CCR MASK
EXCLUSIVE OR
EORA
EORB
A
B
INCLUSIVE OR
ORAA
ORAB
A + (M)
B + (M)
ORCC
OPERATION
(M)
(M)
CCR
A
B
A
B
CCR + MASK
CCR

JUMP AND BRANCH INSTRUCTIONS
FUNCTION
MNEMONIC
OPERATION/BRANCH TEST
NO OPERATION
NOP
PC ADVANCES TO NEXT INST.
JUMP TO ADDRESS
JMP
(M)
PC H , (M+1)
PC L
JUMP TO SUBROUTINE
JSR
PC L
PC H
(M)
(M SP ), SP-1
(M SP ), SP-1
PC H , (M+1)
SP
SP
PC L
RETURN FROM SUBRTN
RTS
BRANCH TO SUBRTN
BRANCH ALWAYS
BRANCH NEVER
SP+1
SP+1
SP,(M
SP,(M
BSR
PC L
PC H
(M)
BRA
BRN
NO TEST
NO TEST, PC
SP )
SP )
(M SP ), SP-1
(M SP ), SP-1
PC H , (M+1)
PC
PC
H
L
SP
SP
PC
NEXT INST.

CONDITION CODE REGISTER INSTRUCTIONS
FUNCTION
CLEAR CARRY
CLEAR INTERRUPT MASK
CLEAR OVERFLOW
SET CARRY
SET INTERRUPT MASK
SET OVERFLOW
ACCUMULATOR A
CCR
CCR
ACCUMULATOR A
MNEMONIC
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
OPERATION
0
C
0
I
0
V
1
C
1
I
1
V
A
CCR
CCR
A
OR CONDITION CODE
ORCC
CCR + OPERAND
AND CONDITION CODE
ANDCC
CCR ^ OPERAND

BLOCK MOVE ROUTINE

WRITE A BLOCK MOVE ROUTINE. THE ROUTINE COPIES DATA FROM MEMORY
LOCATION $5000 TO MEMORY LOCATION $5100. THE ROUTINE WILL END WHEN
A DATA BYTE WITH VALUE OF ZERO IS MOVED.
WRITE YOUR PROGRAM HERE
ORG
SOURCE
FCC
FCB
ORG
$5000
DATA TO MOVE
0
$4000
SUGGESTED PROGRAM STEPS

ORIGINATE DATA AT ADDRESS $4000.
FORM TABLE OF DATA TO BE MOVED
FORM CONSTANT BYTE OF 0.
PROGRAM BEGINS @$4000.
1. INIT SOURCE POINTER T0 $5000.
2. INIT DESTINATION POINTER TO $5100.
3. GET DATA FROM SOURCE ADDRESS.

4. WRITE DATA TO DESTINATION ADDRESS,
LOOP
BEQ
DONE
5. IF DATA MOVED = 0, GO TO STEP 9,

ELSE GO TO 6.
6. INCREMENT SOURCE POINTER.
7. INCREMENT DESTINATION POINTER.
DONE
BRA
LOOP
BRA
DONE
8. GO TO STEP 3.
9. STAY HERE.

CLEAR RAM ROUTINE
Write a routine to clear the HCS12 RAM memory, assume RAM begins at $5000
and ends at $5FFF.


003-HCS12 Instruction Set

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HCS12

HCS12 Technical Training

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

LOAD 16 BIT REG

EXAMPLE: LEAX B,Y

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

STORE 16 BIT REG

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

TRANSFER REG TO REG

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

Bit Manipulation Example: BSET OFFSET,X, #MASK

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

MIN ((A), (M))

MIN ((A), (M))

MAX ((A), (M))

MAX ((A), (M))

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

MIN ((D), (M:M+1))

MAX ((D), (M:M+1))

MAX ((D), (M:M+1))

HCS12 Technical Training

DATA HANDLING INSTRUCTIONS

HCS12 Technical Training

DATA TEST INSTRUCTIONS

HCS12 Technical Training

CONDITIONAL BRANCH INSTRUCTIONS (1 0F 3)

*Use for signed

(L) BCS (BLO)

HCS12 Technical Training

CONDITIONAL BRANCH INSTRUCTIONS (2 0F 3)

DECREMENT & BRANCH

INCREMENT & BRANCH

TEST & BRANCH

IF COUNTER = 0, THEN PC+$0003 + REL

IF COUNTER <>0, THEN PC+$0003 + REL

MOVW $1000, 2,X+

BRANCH IF BITS SET OR CLEAR (3 of 3)

RADIX POINT OF THE RESULT IS TO THE LEFT OF THE MSB

HCS12 Technical Training

ADD WITH CARRY

CONVERTS BINARY ADDITION OF

HCS12 Technical Training

HCS12 Technical Training

RADIX POINT OF THE RESULT IS TO THE RIGHT OF THE LSB

V = 1, IF RESULT > $FFFF FOR UNSIGNED, UNDEFINED IF DIVISOR IS $0000

EXTENDED MULTIPLY AND ACCUMULATE

(M (X) : M (X+1) ) * (M (Y) : M (Y+1) ) + M ~ M+3)

HCS12 Technical Training

HCS12 Technical Training

JUMP AND BRANCH INSTRUCTIONS

PC ADVANCES TO NEXT INST.

RETURN FROM SUBRTN

HCS12 Technical Training

CONDITION CODE REGISTER INSTRUCTIONS

AND CONDITION CODE