CS 162 Computer Architecture

Lecture 1
Instructor: L.N. Bhuyan
www.cs.ucr.edu/~bhuyan/cs162

1999 UCB

Instructor Information
Laxmi Narayan Bhuyan

Office: SURGE 319

E-mail: bhuyan@cs.ucr.edu
Tel: (909) 787-2347

Office Times: W, Th 2-3 pm

1999 UCB

Course Syllabus
Advanced processor design: CPU pipelining, Datapath and Control
Design, Data and Control Hazards: The topics will be covered from
Chapter 6 of the text
Instruction level parallelism, Dynamic scheduling of instructions, Branch
Prediction and Speculation From reference book and papers
VLIW, Multithreading, and Network processor architectures From papers
Basic multiprocessor design: Shared memory and message passing;
Network topologies. The topic will be covered from Chapter 9 of the text.
Main Text: Patterson and Hennessy, Computer Organization and
Design, Morgan Kaufman Publisher
Reference: Hennessy and Patterson, Computer Architecture: A
Quantitative Approach, Morgan Kaufman Publisher

Laboratory Assignments:
(1) Design of ILP-based processor using SimpleScalar
(www.simplescalar.com)
(2) Simulating Intel IXP 1200 network processor using SDK simulator
(3) Performance measurement of IXP 1200-based router

1999 UCB

Course Details
Prerequisite: CS 161 with a grade C or better

Grading: Based on Curve

Test1: 25 points
Test 2: 30 points
Lab: 30 points
Project: 15 points

1999 UCB

Review of CS 161
What is a von-Neumann computer? =>
The Stored Program Concept Sequential
Execution of a program instructions in
binary for storing in memory

Design of an Instruction Set - RISC Vs.

CISC, Examples

Design of CPU Datapath

CPU Control Design (Hardwire vs.
Microprogramming)

Memory Design (Main memory, Cache

Memory, Virtual memory)
5

Input-Output
1999 UCB

MIPS ISA
1. all MIPS instructions are same length
simplifies fetch and decode (steps 1,2)
Intel 80x86 and IBM 360/370 instructions
are variable length, 1-17 bytes

2. few instruction formats in MIPS

source register fields are same place in
all instructions
can read two registers and decode
instruction in the same cycle
Explicit Load/Store instructions for
memory-register operations
6

1999 UCB

Review of CPU Datapath Design

Instruction operation consists of 5 parts,
namely, Fetch (IF), Decode (ID), Execute
(EX), Memory (DM), and Write-back (WB)
stages
Single Cycle Design Big Cycle CPI = 1

Problems: (1) Low frequency meaning less number

of instructions executed per cycle (2) All instns
take same one big cycle

Multicycle Design Small Cycle CPI < 5

Break the datapath to several stages, each taking
one cycle. Frequency is increased and some instns

can finish earlier. Problems: Need extra registers to

separate the stages and control must ensure that
right control signals must be applied to right stage
at the right time => complex control design, but still
manageable in hardware.

1999 UCB

Review: Datapath for MIPS

Stage 5

PC

Instruction
Memory
(Imem)
Stage 1

Registers

Stage 2

ALU

Stage 3

Data
Memory
(Dmem)
Stage 4

Use datapath figure to represent stages

IFtch Dcd Exec Mem WB

Reg

ALU

IM

DM

Reg
1999 UCB

Pipelined Execution IPC= 1

Time
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

Program Flow

To simplify pipeline, every instruction

takes same number of steps, called
stages
9

One clock cycle per stage

1999 UCB

Graphical Pipeline Representation

Time (clock cycles)
ALU

I
n
IM
DM
Reg
Reg
s Load
IM
DM
Reg
Reg
t Add
r.
IM
DM
Reg
Reg
Store
O
IM
DM
Reg
Reg
Sub
r
IM
DM
Reg
Reg
d Or
e
r
(right half highlighted means read, left half write)
ALU

ALU

ALU

ALU

10

1999 UCB

ALU

IM

Reg

DM

Reg

IM

ALU

Reg

DM

Reg

IM

ALU

Reg

Example: Single-cycle vs. Pipelined

time
2

IM

Reg

11

IM

DM

10

12

14

16

18

20

Reg

DM

Reg

Reg

ALU

Reg

ALU

IM

ALU

DM

Reg
1999 UCB

Advanced Architectural Concepts

Can we achieve CPI < 1?
(i.e., can we have IPC > 1?)
State-of-the-Art Microprocessor
Superscalar execution or Instruction
Level Parallelism (ILP)
Deeper Pipeline => Dynamic Branch
Prediction => Speculation => Recovery
Out-of-order Execution => Instruction
Window and Prefetch => Reorder Buffers

VLIW Ex: Intel/HP Titanium

12

1999 UCB

Instruction Level Parallelism (ILP) IPC > 1

Time
IFtch Dcd Exec Mem WB
IFetchDcd Exec Mem WB
IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB
IFtch Dcd Exec Mem WB

Program Flow

ILP = 2

EX: Pentium, SPARC, MIPS 10000, IBM Power PC

13

1999 UCB

Very Large Instruction Word (VLIW) IPC > 1

Time
IFtch Dcd Exec Mem WB
Exec
IFtch Dcd Exec Mem WB
Exec
IFtch Dcd Exec Mem WB
Exec

Program Flow

14

EX: Itanium

1999 UCB