4615-4712 - Chapter 1

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THE ARCHITECTURE OF
8086
CHAPTER 1
The x86 Microprocessor Lyla B Das
Figure 1.1a 8086: INTERNAL

BLOCK DIAGRAM

3
The 8086 microprocessor

has
The execution unit
The bus interface unit
THE EXECUTION UNIT

Has the internal registers, ALU and the control
unit
Fig 1.2 Registers
The scratch pad registers

AX (16 bits) -- AH and AL (each 8 bit)
BX (16 bits) -- BH and BL (each 8 bit)
CX (16 bits) -- CH and CL (each 8 bit)
DX (16 bits) -- DH and DL (each 8 bit)
Pointer and Index

Registers
DI destination index for string operations
SI source index for string operations
SP stack pointer for accessing stack top
BP base pointer for accessing any location
in stack
IP instruction pointer-points to the next
instruction to be executed
Fig 1.3 Flag Register
FLAGS
CONDITIONAL FLAGS
CONTROL FLAGS
OF =
Overflow flag
DF = Direction Flag
SF =
ZF =
Sign Flag
Zero Flag
Auxiliary carry Flag
Parity Flag
Carry Flag
AF =
PF =
CF =
IF = Interrupt Flag
TF = Trap Flag
10
Example 1.1
Find the status of the flags CF ,SF, AF after
the following instructions are executed

MOV AL,35H
ADD
AL,0CEH
11
Example 1.2
Show the effect of the following instructions
on the CF,ZF and OF bits of the flag register.
MOV BX,45ECH
ADD
BX,7723H
12
Example 1.3
Assuming we are adding signed 8 bit
numbers, how is the result of the following
addition to be interpreted?
MOV AL,125
ADD AL,75
13
THE BUS INTERFACE UNIT

is responsible for address calculations
pre-fetching instructions for the queue
and sequencing instructions one by one
14
THE INSTRUCTION QUEUE

There is a queue which fetches instructions
ahead of the execution time

and places them in a six byte first in first out
(FIFO) queue
Pre-fetching belongs to a class of ideas called
pipelining, which means that both execution
and fetching take place at the same time.
15
MEMORY SEGMENTATION
Each address is 20 bit
But address registers are only 16 bits long
There are four types of memory segments

They cater to data, code, stack and another
data segment called the extra segment
16
Segment Registers (16 bits long)

CS code segment register
DS data segment register
SS stack segment register
ES extra segment register
17
18
Figure 1.4 Calculation of a physical

address from the logical address for a
data segment
Figure 1.5 Segment registers and

corresponding segments
19
Segments and corresponding

registers
Code segment ---- Instruction pointer (IP)
Stack segment . Stack pointer (SP)
20
Arithmetic Logic Unit

performs all arithmetic and logic
computations.
is the most important unit of the processor
instructions that are fetched and decoded, are
executed in the ALU.
the ALU has direct access to the general
purpose registers and flags.
21
Figure 1.6 Stack and physical

address of the top of stack
22
Effective address
How is it calculated?
What is its relationship with the physical
address?
23
Table 1.1 Segments and

Corresponding Registers Used for
Specifying Off Sets
24
Example 1.4
The content of DS is 345BH. The amount of
data that is to be stored in the data segment

is 12K bytes. Where in memory, will this
segment be located?
25
Example 1.4 Solution

The base address of the segment is 345B0H
The last address will have an offset of 12K
from the base address .

1K = 1024 bytes
12 K = 12 1024 = 12228 = 3000H
The last address of the segment = 345B0H +
3000H = 375B0H
26
Example 1.5
The contents of the following segment registers
are as given
CS =1111H, DS = 3333H, SS = 2526H
IP = 1232H, SP = 1100H ,
offset in data segment = 0020H
Calculate the corresponding physical addresses
for the addressed byte in a) CS b) SS and c) DS
27
Example 1.5 Solution

The address of the next instruction is given by
11110H + 1232H = 12342H

The physical address of the stack top is
25260H + 1100H = 26350H
The physical address of the data in the data
segment is calculated as 33330H + 0020H =
33350H
28
Advantages of Segmentation
All address registers are only 16 bit long,
though the physical address is 20 bits

All addresses are re-locatable
29
Memory Organization Little

Endian
In the case of a word of data stored in memory
if the lower byte is in the lower address
and the higher byte is in the higher address
it is called the little endian format
30
Figure 1.7 Little Endian Format
31
ADDRESSING MODES
The way in which operands are specified in an
assembly language instruction is called its

addressing mode
For a move instruction, the format is
MOV destination, source
32
Addressing modes basic

assumptions
The operands can be in registers, in memory,

or may be in the instruction itself. But the
8086 does not have an addressing mode in
which both operands are in memory locations
In the case of two operands, one of them can
be in memory, but the other will have to be
placed in a register .
Data types should match i.e., the source and
destination should both be either bytes or
words
33
Register Addressing
Here both the source and destination are
registers
MOV AL, AH
MOV CH, BL
MOV SI, BX
MOV ES,AX
34
Immediate Addressing
Here, the source will be a constant data
MOV AL, 45H
MOV BX, 34E3H
MOV CL.Q
MOV PRICE,40
MOV NUMS, 0FC6H
PRICE and NUMS are labels for memory
addresses
35
Direct Addressing
Here either the source or the destination will
be a memory address
MOV AX,[2345H]
MOV [1089H],AL
MOV AX , PRICE
MOV COST,AL
PRICE and COST are labels for memory
addresses
36
Register Indirect Addressing

In this mode, the address of the data is held
in a register
Effective address
EA = EA = { [BX] / [DI] /[SI]}
37
Register Indirect Addressing

Contd.
MOV AL,[BX]
MOV [SI], CL
MOV [DI],AX
38
Example 1.6
Show the location of data in memory, after

the execution of each of these instructions,
if the content of registers are as given
DS =
MOV
MOV
MOV
1112H, AX = EE78H and BX = 3400H

[0422H], AL
[0424H], AX
[BX], AX
39
Register Relative Addressing

In relative addressing mode, a number or
displacement is part of the effective address

EA = {[BX] /[DI] /[SI] /[BP]} + 8 bit or 16 bit
displacement
The displacement can be a 16 bit
signed/unsigned number or an 8 bit sign
extended number
40
Register Relative Addressing

Contd.
MOV CL, 10[BX]
Thus the effective address is [BX + 10 ].
41
Based Indexed Mode

In this mode, an index register and a base
register together carry the effective address .

The content of these two registers are added
and called the effective address.
MOV AL,[BX][SI]
MOV [BX][DI],CX
42
Relative Based Indexed Mode

The effective address is the sum of the two
registers and a displacement .

MOV DL ,5[BX][DI]
MOV 5[BP][SI], AX
MOV CL,COST[BX[[SI]
43
Example 1.7
Find the address of physical memory for
the following instructions if the content
of the required registers are as given below
SS = 2344 H, DS = 4022H ,
BX = 0200H, BP = 1402H, SI = 4442H
i) MOV CL,1234H[SI]
i) MOV AL,5[SI[[BP]
44
Table 1.2 : Effective Address and Referred

Segments for Various Memory Based
Addressing Modes
45
Segment Override
MOV AL, ES: [BX]
MOV DS: [BP+7], BL
MOV AX, CS:[BX ]
46

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The x86 Microprocessor Lyla B Das

Copyright Dorling Kindersley India Pvt Ltd

Figure 1.1a 8086: INTERNAL

The x86 Microprocessor Lyla B Das

The x86 Microprocessor Lyla B Das

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The 8086 microprocessor

The x86 Microprocessor Lyla B Das

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THE EXECUTION UNIT

The x86 Microprocessor Lyla B Das

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Fig 1.2 Registers

The x86 Microprocessor Lyla B Das

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The scratch pad registers

The x86 Microprocessor Lyla B Das

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Pointer and Index

The x86 Microprocessor Lyla B Das

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Fig 1.3 Flag Register

The x86 Microprocessor Lyla B Das

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The x86 Microprocessor Lyla B Das

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the following instructions are executed

The x86 Microprocessor Lyla B Das

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on the CF,ZF and OF bits of the flag register.

The x86 Microprocessor Lyla B Das

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The x86 Microprocessor Lyla B Das

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THE BUS INTERFACE UNIT

The x86 Microprocessor Lyla B Das

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THE INSTRUCTION QUEUE

ahead of the execution time

The x86 Microprocessor Lyla B Das

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There are four types of memory segments

The x86 Microprocessor Lyla B Das

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Segment Registers (16 bits long)

The x86 Microprocessor Lyla B Das

The x86 Microprocessor Lyla B Das

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Figure 1.4 Calculation of a physical

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Figure 1.5 Segment registers and

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Segments and corresponding

The x86 Microprocessor Lyla B Das

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Arithmetic Logic Unit

The x86 Microprocessor Lyla B Das

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Figure 1.6 Stack and physical

The x86 Microprocessor Lyla B Das

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