FET a three-terminal voltage-controlled

device used in amplification and switching

application.
Field effect transistors controls current by
voltage applied to the gate. The FETs
major advantage over the BJT is high input
resistance.
2 basic type of FET: JFET and MOSFET

The junction field effect transistor, like a BJT, controls

current flow. The difference is the way this is
accomplished. The JFET uses voltage to control
the current flow. As you will recall the transistor
uses current flow through the base-emitter junction to
control current. JFETs can be used as an amplifier just
like the BJT.

VGG voltage levels control current flow in theVDD, RD

circuit.

 The terminals of a JFET are the source, gate,

and drain.
A JFET can be either p channel or n channel.

 VDD provide a drain-to-source voltage.

VGG sets the reverse-bias voltage between gate and
source. JFET is always operated with gate-source pn
junction reverse-biased. Reverse-biasing of the gatesource junction with a ve gate voltage produces a
depletion region along pn junction.

JFET Biasing
Gate-to-source junction of JFET always reverse-

biased under normal condition.

Gate-to-source junction never allowed to
become forward-biased because the gate
material is not designed to handle any
significant amount of current may destroy
the component.

Effects with a VGS of 0V, this is produced by shorting

the gate to source junction.

From point A to B, ID increases proportionally with

increases of VDD (VDS increases as VDD increases).

This is called the ohmic region (point A to B).
At point B, the curve levels off and ID becomes
constant. The point when ID ceases to increase
regardless of VDD increases is called the pinchoff voltage, VP (point B). This current is called
maximum drain current (IDSS) and always
specified for the condition, VGS=0V. This area is
called constant-current area.
Breakdown (point C) occur when ID begins to
increase rapidly with any increase in VDS.

Set of curves with increased voltage applied to the gate,

ID decrease and JFET reaches pinch-off at values of VDS
less than VP.

 As VGS is increased ID will decrease. The point that ID

ceases increase is called cutoff. The amount of VGS
required to do this is called the cutoff voltage
(VGS(of ) ).
The more negative VGS, the smaller ID becomes. When
VGS has sufficiently large negative value, ID is reduced
to zero.
Note:
that pinch-off voltage
(Vp) and cutoff voltage
(VGS(of)) are both the same
value only opposite polarity.

JFET Transfer Characteristic

For n-channel JFET, VGS(off) is negative and for p-

channel, VGS(off) is positive.

Bottom end of the curve is at a point on VGS axis
equal to VGS(off) and the top end of the curve is at
a point on ID axis equal to IDSS (shorted-gate drain
current rating of the device).
The operating limits of JFET are:
ID=0
when VGS=VGS(off)
ID=IDSS
when VGS = 0
Transfer characteristic curve can be developed
from drain characteristic curves by plotting
values of ID for the values of VGS taken from the
family of drain curves at pinch-off.

The transfer characteristic curve illustrates the control VGS

has on ID from cutoff (VGS(of) ) to pinchoff (VP). Note the
parabolic shape. The formula below can be used to
determine drain current. All these values are usually
available from data sheet.
ID = IDSS(1 - VGS/VGS(off))2

Forward transfer conductance, gm of JFETs is

sometimes considered. It is the changes in ID based on
changes in VGS with VDS is constant.
Input resistance for a JFET is high since the gate -source
junction is reverse biased, however the capacitive effects
can offset this advantage particularly at high
frequencies.
The value is larger at the top of the curve (near
VGS=0) but become smaller as you increase VGS
(near VGS(off)).

Transconductance

Forward transfer conductance referred to as

gm = ID /VGS.
At VGS =0, the parameter is known as minimum
transfer conductance, gmo and can be
calculated using this equation:
gmo = 2IDSS/|VGS(off)| and gm = gmo(1 - VGS/VGS(off))
gmo can be read from the
datasheet as gfs or yfs and
sometimes written as Forward
Transfer Admittance.

The internal input resistance can be calculated at

different VGS :
RIN=|VGS/IGSS|
As IGSS increases with temperature, RIN will decrease.

JFET must be biased for operation and most cases

the ideal Q-point will be the middle of the transfer
characteristic curve which is about half of the IDSS.
4 types of bias method are self-bias, gate-bias,
voltage-divider bias and current-source bias.

 Self-bias is the most common type of biasing method

for JFETs.
No voltage applied to the gate, VG=0V. However, the
voltage from gate to source (VGS) will be negative for n
channel and positive for p channel to keep the junction
reverse biased.
Using a source resistor to reverse biased the JFET gate.
The gate is returned to ground via RG, and RS has been
added to source circuit.
This voltage can be determined using the formulas
below. ID = IS for all JFET circuits. VG=0 and VS=IDRS.
VGS = VG - VS
(n channel) VGS = 0-IDRS =-IDRS

JFET Biasing- Self bias

JFET Biasing self bias

For p-channel it is the same as n-channel except

for opposite polarity voltages.

The drain voltage with respect to ground is:
VD = VDD IDRD
Since VS = IDRS, VDS is:
VDS = VD VS = VDD ID(RD+RS)

 Voltage-divider bias can be used

to bias a JFET. R1 and R2 are used to
keep the gate-source junction in
reverse bias. Operation is no different
from self-bias. Determining VGS for a
JFET voltage-divider circuit with
givenVD can be calculated with the
formulas below.
Source voltage,VS = IDRS
Gate voltage, VG
=(R2/R1+R2)VDD
Gate-to-source voltage.VGS=VG
VS
Source voltage, V = V - V

JFET Biasing Current Source Bias

Current source bias provides high Q-point

stability by making value of ID independently of

JFET.
JFET drain current equals BJT collector current.
IDQ = IC
Advantage: provide the most stable Q-point
value of ID.
Disadvantage: circuit complexity makes it
undesirable for most applications.

JFET Biasing- Current source

bias

Transfer characteristics can vary for JFETs of

the same type. This would adversely affect
the Q-point for self-bias analysis. Q-point is
much more stable using voltage-divider bias
and current source bias.