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DECODER and

QUICK RECAP

WHY THIS QUIZ IS


IMPORTANT

DECODER
N input and M Out put
M=2n

N=2

MAIN DECODER HON

M=2n
M=22=4

3x___ Decoder

N=3

MAIN DECODER HON

M=2n
M=23=8

As its name indicates, a decoder is a


circuit component that decodes an
input code
each output line equals 1 at only one
input combination but is equal to 0 at
all other combinations
In other words, each decoder output
corresponds to a minterm of the n
input variables

DESIGN 2x$
AB
AB
AB

AB

THE CIRCUIT
0

Lets try
LETS TRY TO GENERATE
TABLE
for 00

1 AND
1=1
1

1
1

0
1
0
0
0

1 AND
0=0=
1 AND
0=0
0 AND
0=0

A B
0
0
1
1

0
1
0
1

o1 o2 o3 o4
1

The enable input in


decoders
If the enable E
is zero, then all outputs are zero
regardless of the input values.
is one, then the decoder performs its
normal operation.

If E=1
1
1
1
1

If E=0
0
0
0
0

Decoder

2-to-4,
3-to-8,

n-to-2n

S2

S1

S0

3:8
dec

O0
O1
O2
O3
O4
O5
O6
O7

Enb

ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC

B C O0 O1 O2 O3 O4 O5 O6 O7

13

Decoder

14

Example: Construct a 3-to-8 decoder


using two 2-to-4 decoders with enable
Enable=0
inputs.Q0 Q1 Q2 Q3 Q4 Q5 Q6
s1 s0
A

Q7
0
0
0
1
1
0
1
1
s1 s0
0
0
0
1
1
0
1
1

Q0 Q1 Q2
0 Q1 Q2
Q0
0
Q0 Q1 Q2
0
Q0 Q1 Q2
0

Q3

Q3

Q3

Q3

Q0 Q1 Q2 Q3
Q7
0 0
Q7
0 0
Q7
0 0
Q7
0 0
Q7

Q4 Q5 Q6
Q4 Q5 Q6

Q4 Q5 Q6

0
0

0
0

Q4 Q5 Q6
Q4 Q5 Q6

Example: Construct a 3-to-8 decoder


using two 2-to-4 decoders with enable
Enable=1
inputs.Q0 Q1 Q2 Q3 Q4 Q5 Q6
s1 s0
A

Q7
0
0
0
1
1
0
1
1
s1 s0
0
0
0
1
1
0
1
1

Q0 Q1 Q2
0 Q1 Q2
Q0
0
Q0 Q1 Q2
0
Q0 Q1 Q2
0

Q3

Q3

Q3

Q3

Q0 Q1 Q2 Q3
Q7
0 0
Q7
0 0
Q7
0 0
Q7
0 0
Q7

Q4 Q5 Q6
Q4 Q5 Q6

Q4 Q5 Q6

0
0

0
0

Q4 Q5 Q6
Q4 Q5 Q6

Decoder design with NAND gates


Some decoders are constructed with
NAND rather than AND gates.
In this case, all decoder outputs will
be 1s except the one corresponding
to the input code which will be 0.

Design example: addition


Lets make a circuit that adds three
1-bit inputs X, Y and Z.
We will need two bits to represent
the total; lets call them C and S, for
carry and sum. Note that C and S
are two separate functions of the
same inputs X, Y and Z.
Here are a truth table and sum-ofminterms equations for C and S.

0 + 1 + 1 = 10

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

C(X,Y,Z) = m(3,5,6,7)
S(X,Y,Z) = m(1,2,4,7)

1 + 1 + 1 = 11

Decoder-based adder
Here, two 3-to-8 decoders implement C and S as sums of minterms.

C(X,Y,Z) = m(3,5,6,7)
S(X,Y,Z) = m(1,2,4,7)

The +5V symbol (5 volts) is how you represent a constant 1 or true in


LogicWorks. We use it here so the decoders are always active.

Design a two bit comparator , using suitable decoder which provides 1


as output only if
A=B
A>B

A=B

A>B

A1

A2

B1

B2

A=B(A,B) = m(0,5,10,15)
A>B(A,B) = m(4,8,9,12,13,14)

Design Using Decoder


F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

A=B(A,B) = m(0,5,10,15)

A1
A2

4:16
dec

B1
B2

Enb

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

ABCD
A BCD
ABCD
ABCD
ABCD
ABCD
ABCD
A BCD
A BCD
A BCD
A BCD
A BCD
A B CD
A B CD
A B C D
AB C D

Encoders
An encoder performs the inverse
operation of a decoder,
It has 2n inputs, and n output lines.
Only one input can be logic 1 at any
given time (active input). All other
inputs must be 0s.

Example

S2

S1

S0

O0
O1
O2
O3
3:8
decoder O4
O5

I0
I1
I2
I3
I4
I5

O6
O7

I6
I7

Z2

Z1
8:3
encoder
Z0

B
C

Encoder Circuit Design


Example:

8-3 Binary Encoder

30

A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

Note that not all input combinations


are valid.
Valid combinations are those which
have exactly one input equal to logic
1 while all other inputs are logic 0s.
Since, the number of inputs = 8, Kmaps cannot be used to derive the
output Boolean expressions.

Application

The number of inputs: large


fewer lines
32

Limitations
Only one input can be active at any
given time
Can we Design a Circuit which can have
two ones as input

Priority Encoders
Use a Priority Encoder which
produces the output corresponding to
the input with higher priority.
In the example, if E3 = E6 = 1, the
output corresponding to E6 will be
produced since E6 has higher priority
than E3.

I1

i2

i3
o1 o2

i4