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And, Finally...
The Stack
Stack data structure
Interrupt I/O (again!)
Arithmetic using a stack
ASCII-Decimal Conversion
Converting between human-friendly and
computer-friendly representations
Interrupt-Driven I/O
Efficient, device-controlled interactions
10-2
Stacks
Abstract Data Structures
are defined simply by the rules for inserting and extracting data
A Physical Stack
A coin holder as a stack
Initial State
(Empty)
1995
1996
1998
1982
1995
1998
1982
1995
After
One Push
After Three
More Pushes
After
One Pop
A Hardware Implementation
Data items move between registers
Note that the Top Of Stack is always in the same place.
Empty:
Yes
//////
//////
//////
//////
//////
Initial State
Empty:
TOP
No
#18
//////
//////
//////
//////
After
One Push
Empty:
TOP
No
#12
#5
#31
#18
//////
After Three
More Pushes
Empty:
TOP
No
#31
#18
//////
//////
//////
TOP
After
Two Pops
10-5
A Software Implementation
Data items don't move in memory,
just our idea about there the TOP of the stack is.
TOP
//////
//////
//////
//////
//////
x3FFF
#18
//////
//////
//////
//////
R6
Initial State
By convention, R6
x4000
After
One Push
TOP
R6
#18
#31
#5
#12
//////
x4003
TOP
R6
After Three
More Pushes
#18
#31
#5
#12
//////
x4001
TOP
R6
After
Two Pops
10-6
R6, R6, #1
R0, R6, #0
LDR
ADD
Pop
10-7
10 - 8
LD R1, EMPTY ;
ADD R2, R6, R1 ;
BRz FAIL
;
LDR R0, R6, #0
ADD R6, R6, #-1
AND R5, R5, #0 ;
RET
FAIL AND R5, R5, #0 ;
ADD R5, R5, #1
RET
EMPTY .FILL xC001
EMPTY = -x3FFF
Compare stack pointer
with x3FFF
SUCCESS: R5 = 0
FAIL: R5 = 1
10-9
FAIL
MAX
LD R1, MAX
ADD R2, R6,
BRz FAIL
ADD R6, R6,
STR R0, R6,
AND R5, R5,
RET
AND R5, R5,
ADD R5, R5,
RET
.FILL xBFFC
; MAX = -x4004
R1 ; Compare stack pointer
; with x3FFF
#1
#0
#0 ; SUCCESS: R5 = 0
#0 ; FAIL: R5 = 1
#1
10-10
10-11
x23
R1, R0, #0
x23
R0, R1, R0
x21
x25
;
;
;
;
;
;
ASCII to Binary
Useful to deal with mult-digit decimal numbers
Assume we've read three ASCII digits (e.g., "259")
into a memory buffer.
How do we convert this to a number
we can use?
x32
x35
x39
'2'
'5'
'9'
10-13
0 x 100 = 0
1 x 100 = 100
2 x 100 = 200
3 x 100 = 300
10-14
10-15
10-16
Conversion Routine (2 of 3)
ADD
BRz
ADD
LDR
ADD
LEA
ADD
LDR
ADD
R4,
R4,
R5,
R5,
R4,
R0,
; load digit
; convert to number
; multiply by 10
ADD
BRz
ADD
;
R2, #0
R4, R3
Lookup10
R5, R4
R5, #0
R0, R4
;
;
;
;
;
Conversion Routine (3 of 3)
LDR
ADD
LEA
ADD
LDR
ADD
;
DoneAtoB
NegZero
ASCIIBUF
Lookup10
...
Lookup100
RET
.FILL
.BLKW
.FILL
.FILL
.FILL
R4,
R4,
R5,
R5,
R4,
R0,
R2, #0
; load digit
R4, R3
; convert to number
Lookup100 ; multiply by 100
R5, R4
R5, #0
R0, R4
; adds 100's contrib
xFFD0
4
0
10
20
; -x30
.FILL 0
.FILL 100
...
10-18
10-19
10-20
Conversion (2 of 3)
Begin100
Loop100
End100
LD R2, ASCIIoffset
LD R3, Neg100
ADD R0, R0, R3
BRn End100
ADD R2, R2, #1 ; add one to digit
BRnzp Loop100
STR R2, R1, #1 ; store ASCII 100's digit
LD R3, Pos100
ADD R0, R0, R3 ; restore last subtract
;
Loop10
LD R2, ASCIIoffset
LD R3, Neg10
ADD R0, R0, R3
BRn End10
ADD R2, R2, #1 ; add one to digit
BRnzp Loop10
10-21
Conversion Code (3 of 3)
End10
;
LD R2, ASCIIoffset
ADD R2, R2, R0 ; convert one's digit
STR R2, R1, #3 ; store one's digit
RET
;
ASCIIplus
ASCIIneg
ASCIIoffset
Neg100
Pos100
Neg10
.FILL
.FILL
.FILL
.FILL
.FILL
.FILL
x2B
x2D
x30
xFF9C
100
xFFF6
;
;
;
;
plus sign
neg sign
zero
-100
; -10
10-22
Interrupt-Driven I/O
Timing of I/O controlled by device
tells the processor when something interesting happens
Example: when character is entered on keyboard
Example: when monitor is ready for next character
processor interrupts its normal instruction processing
and executes a service routine (like a TRAP)
figure out what device is causing the interrupt
execute routine to deal with event
resume execution
no need for processor to poll device, waiting for events
can perform other useful work
10-23
10-24
Interrupt vector
8-bit signal for device to identify itself
(may be different for other processors)
also used as entry into system control block,
which gives starting address of Interrupt Service Routine (ISR)
like TRAP
INT
CPU
INTAC
K
Controller
Device
vector
10-25
stack
More Control
At the device
control register has Interrupt Enable bit
must be set for interrupt to be generated
interrupt enable
ready
KBSR
interrupt signal
to processor
At the processor
sometimes have Interrupt Mask register (LC-3 does not)
when set, processor ignores INT signal
why?
Example: dont want to interrupt while in ISR
10-27
Example (1)
Program A
//////
//////
//////
//////
//////
R6
PC
x3006
ADD
x3006
Example (2)
Program A
//////
x3007
R6
CC for ADD
//////
//////
PC
ISR for
Device B
x6200
x3006
ADD
x6210
RTI
x6200
10-29
Example (3)
Program A
//////
x3007
R6
CC for ADD
//////
//////
PC
ISR for
Device B
x6200
x3006
ADD
x6202
AND
x6210
RTI
x6203
Example (4)
Program A
//////
x3007
CC for ADD
x6203
R6
CC for AND
PC
ISR for
Device B
x6200
x3006
ADD
x6202
AND
ISR for
Device C
x6210
RTI
x6300
x6300
x6315
RTI
10-31
Example (5)
Program A
//////
x3007
R6
CC for ADD
x6203
CC for AND
PC
ISR for
Device B
x6200
x3006
ADD
x6202
AND
ISR for
Device C
x6210
RTI
x6300
x6203
x6315
RTI
Example (6)
Program A
//////
x3007
R6
CC for ADD
x6203
CC for AND
PC
ISR for
Device B
x6200
x3006
ADD
x6202
AND
ISR for
Device C
x6210
RTI
x6300
x3007
x6315
RTI
10-33
R6
//////
x3007
CC for ADD
x6203
CC for AND
PC
x3007
Example
ISR for
Device B
x6200
x3006
ADD
1
4
x6202
AND
2
ISR for
Device C
x6210
RTI
x6300
3
x6315
RTI
10-34