Académique Documents
Professionnel Documents
Culture Documents
Structures de bases
Synthse doprateurs standards
Prsentation
Electronique reprogrammable
Apparition des premiers circuits vers les annes 70: premiers PLD-> PAL,
GAL
Evolution vers composants plus complexes: CPLD, FPGA
Diffrentes technologies pour la programmation des connexions
Permanents , Volatiles statiques, Volatiles
Capacit de programmation In-Situ
composants dits ISP via interface JTAG
Connexions programmables
Introduction
Deux formes canoniques pour les quations logiques
Somme de produits S=a.b+ c.d
Produits de somme
S=(z+f).(e +x)
Connexions programmables
ET cabl
Reprsentation
standard
OU cabl
xPLD
Simple Programme Logic Device
Composants simples
rseau ET/OU programmable ou fixe
PAL (OTP en gnral), GAL reprogrammable
Diffrentes familles en
fonction des ressources
rajouts par le constructeurs
FPGA
Field Programmable Grid Array
Granularit plus fine que les CPLD ( macrocellules - complexes mais + nombreuses)
Intgration matrielle de composants supplmentaires
Exemple de rfrence
Famille Cyclone (FPGA Low Cost
dALTERA)
Concurrent: Spartan3 (chez Xilinx)
FPGA
La carte DE2 (utilis en TP)
Specifications
FPGA
Cyclone II EP2C35F672C6 FPGA and
EPCS16 serial configuration device
I/O Devices
Built-in USB Blaster for FPGA configuration
10/100 Ethernet, RS-232, Infrared port
Video Out (VGA 10-bit DAC)
Video In (NTSC/PAL/Multi-format)
USB 2.0 (type A and type B)
PS/2 mouse or keyboard port
Line-in, Line-out, microphone-in
(24-bit audio CODEC)
Expansion headers (76 signal pins)
Memory
8-MB SDRAM, 512-KB SRAM, 4-MB Flash
SD memory card slot
Switches, LEDs, Displays, and Clocks
18 toggle switches
4 debounced pushbutton switches
18 red LEDs, 9 green LEDs
Eight 7-segment displays
16 x 2 LCD display
27-MHz and 50-MHz oscillators, external SMA clock input
VHDL introduction
Programmation ou description?
Les objectifs du langage VHDL
Conception de circuits intgrs reconfigurable ou non (ASIC, FPGA) :
SYNTHESE
Mise au point de modle de simulations numriques (circuits virtuels) :
MODELISATION
Synthse ou modlisation
Nous nous
focaliserons
dans ce cours
la synthse
uniquement
Notre cible en
TP: FPGA
Cyclone 2 sur
la carte DE2
entity
Flot de conception
Un outils de dveloppement: Quartus II dAltera
Logique combinatoire
Logique squentielle
Des exemples:
Multiplexeurs
Additionneurs
Dcodeur 7 segements
Encodeurs de priorit
Des exemples:
Compteurs
Registres dcalage
Machine dtat (automate)
10
Il faut un
SIGNAL
ET4 est un
composant
(entity+architecture)
On crera 1 composant
ET2 (entity+architecture)
Utilis 3 fois pour dcrire
ET4
11
Sorties pilotant
les Leds de
lafficheur 1
12
La librairie IEEE
A mettre au dbut de votre description
Pour rajouter les types tendues std_logic et std_logic_vector
use IEEE.STD_LOGIC_1164.all;
13
IEEE.std_logic_unsigned.all et
IEEE.std_logic_arith.all sont danciennes
bibliothques
IEEE.numeric_std.all;
De convertir des signed ou unsigned en std_logic_vector
IEEE.std_logic_arith.all;
LEDG(3 downto 0)<=std_logic_vector(tempo);
De redimensionner des vecteurs
Alternative resize
A<=resize(signed(SW(LARG downto 1)),LARG+1);
De travailler avec les oprateurs arithmtiques standart Recopie du bit bit de poids forts
A<= A(3)&A
de mlanger des entiers avec des std_logic_vector: A<= A +1;
14
Caractres: 0, x,a,%
Ne pas confondre 1 bit
Chanes: 11110101,xx,bonjour,$@&
Chanes de bits: B0010_1101, X 2D, O 055 exemple 0 ou 1
Dcimaux:27, -5, 4e3, 76_562, 4.25
Avec un vecteur de bits
Bass: 2#1001#, 8#65_07, 16#C5#e2
11 ou 1101110
Les oprateurs
Logiques (boolean, bit, std_ulogic)
AND, OR, NAND, NOR, XOR, NOT
Arithmtiques
+ -
** MOD
REM
15
Exemple 2
library IEEE;
use IEEE.std_logic_1164.all;
entity example is
port(
E:IN std_logic_vector(2 downto 0);
S1:OUT std_logic; --1 fil
S2,S3:OUT std_logic_vector(3 downto 1); --3 fils
S1[3:1]
S4:OUT std_logic_vector(2 downto 0)
);
end example;
--definition de l'architecture
architecture arch_example of example is
begin
S1<='0';
S2<='1'& E(1 downto 0);
-- operateur COLLER (ou CONCATENE)
-- S2(3)
S2(2)
S2(1)
-- '1'
E(1)
&
E(0)
S3<="101";
S4<= "111" XOR E; --manip sur les bus directement
end arch_example;
16
signal <=
Structure WHEN/ELSE
---- Solution 1: with WHEN/ELSE ------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY encoder IS
6 PORT ( x: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
7 y: OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
8 END encoder;
9 --------------------------------------------10 ARCHITECTURE encoder1 OF encoder IS
11 BEGIN
12 y <= "00" WHEN x="0001" ELSE
13
"01" WHEN x="0010" ELSE
14
"10" WHEN x="0100" ELSE
15
"11" WHEN x="1000" ELSE
20
"ZZZ";
21 END encoder1;
22 ---------------------------------------------
Exemple dapplication:
encodeur clavier pour PIC
Intrt: rduire le nombre dentre du PIC
17
Autre possibilt:
std_logic_vector(1 downto 0)
18
ou
Full Adder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fa IS PORT (
Ci, X, Y: IN STD_LOGIC;
S, Cout: OUT STD_LOGIC);
END fa;
ARCHITECTURE Dataflow OF fa IS
BEGIN
Cout <= (X AND Y) OR (Ci AND (X XOR Y));
S <= X XOR Y XOR Ci;
END Dataflow;
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component add1full is
port(
Ci:IN std_logic;
X,Y:IN std_logic;
S,Cout:OUT std_logic
);
end component add1full;
-- declaration des fils internes pour le report carry
signal Fil1,Fil2,Fil3:std_logic;
begin
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Notre ET4
ENTITY ET4 IS
--librairie pour inclure type std_logic
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY ET2 IS
PORT
(
A,B: IN
S: OUT
);
PORT
(X1,X2,X3,X4
: IN
STD_LOGIC;
Y: OUT
);
STD_LOGIC;
STD_LOGIC
END ET2;
ARCHITECTURE arch_ET2 OF ET2 IS
BEGIN
S<= A and B;
END arch_ET2;
END ET4;
On
dclare
ET2
STD_LOGIC
fils de
connexions
INTERNES
PORT MAP
pour
placement et
connexion
21
Squelette de
description
VHDL
--les libraries
library IEEE;
use IEEE.std_logic_1164.all;
.
ENTITY LENIVEAUTOP (
..)
End ENTITY
ARCHITECTURE ..
COMPONENT Truc
END COMPONENT
COMPONENT Machin
END COMPONENT
Dclaration de
composants crs
SIGNAL: .
SIGNAL: ..
XX<=1110;
YY<= A AND B;
U1: Truc PORT MAP( .);
S<= 10 when (A=B) else
00;
U2: Machin PORT MAP( .);
Utilisation des
ressources
disponibles
22
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
Cration de
nouveaux types:
TYPE
Tableau: ARRAY
--definition de l'architecture
architecture arch_dec_7seg_v1 of decod7seg is
-- definition d'un nouveau type
-- tableau de 16 elements de 7 bits
type ROM is array(15 downto 0) of std_logic_vector(6 downto 0);
--initialisaion du tableau
-- tableau vu comme une memoire(LUT)
signal LUT:ROM:=(
"1000000","1111001","0100100","0110000","0011001","0010010","000
0010",
"1111000","0000000","0011000","0001000","0000011","1000110","010
0001",
Carte DE2:
Anode commune
Segment actif 0
Brochage: voir p31 du manuel
"0000110","0001110");
begin
-- pour indexer tableau il faut un entier
-- fonction de conversion conv_integer dans
IEEE.std_logic_unsigned.all
oSeg<=LUT(conv_integer(iDigit));
23
24
Slection Op
2 LIBRARY ieee;
arithmtique/logique
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_unsigned.all;
5 ---------------------------------------------6 ENTITY ALU IS
7 PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
8 sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
9 cin: IN STD_LOGIC;
10 y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
11 END ALU;
12 ---------------------------------------------13 ARCHITECTURE dataflow OF ALU IS
14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0);
15 BEGIN
16 ----- Arithmetic unit: -----17 WITH sel(2 DOWNTO 0) SELECT
18 arith <=
a WHEN "000",
19
a+1 WHEN "001",
20
a-1 WHEN "010",
21
b WHEN "011",
22
b+1 WHEN "100",
b-1 WHEN "101",
24
a+b WHEN "110",
25
a+b+cin WHEN OTHERS;
25
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.all;
3 ---------------------------------------------4 ENTITY tri_state IS
5 PORT ( ena: IN STD_LOGIC;
6 input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7 output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
8 END tri_state;
9 ---------------------------------------------10 ARCHITECTURE tri_state OF tri_state IS
11 BEGIN
12 output <= input WHEN (ena='0') ELSE
13
(OTHERS => 'Z');
14 END tri_state;
15 ----------------------------------------------
26
Le PROCESS est activ lors dun changement dtat dun des signaux de la
liste de sensibilit
Une fois dans le PROCESS le droulement est SEQUENTIELLE
Les instructions utilisables dans un PROCESS sont SPECIFIQUE ( pas de
when/else par exemple)
Les signaux sont mis jour uniquement la fin du process
critures
alternatives
process
begin
q <= d;
wait until Reloj = 1;
end process;
Process
begin
c <= a and b;
wait on a, b;
end process;
Process(a,b)
begin
c <= a and b;
end process;
27
Processus activ
28
Autre faon:
Process(CLK)
Begin
If (CLK=1) then
Q<=D;
End if;
End process;
29
process(horl)
if (horlevent and horl = 1) then
if (ena = 1 ) then
contenu_registre <= valeur_in;
end if;
end if;
end process;
30
process (CLK)
Begin
if (CLK'event and CLK ='1') then
if (RESET =1) then
S <= 0;
elsif (SET =1)then Actif 1 ici pour
S <= 1;
lexemple
else
S <= D;
end if;
end if;
end process ;
31
32
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity CMP4BITSRET is
PORT (
RESET, CLOCK : in std_logic;
RET : out std_logic;
Q : out std_logic_vector (3 downto 0));
end CMP4BITSRET;
33
SOLUTION 2:
process (RESET,CLOCK)
begin
if RESET='1' then
CMP <= "0000";
elsif (CLOCK ='1' and
CLOCK'event) then
CMP <= CMP + 1;
Je dcris le
end if;
combinatoire HORS
end process;
du PROCESS
-- Validation de la retenue
RET <= '1' when (CMP = "1111")
else '0';
34
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity CMP4BITS is
PORT (
CLOCK : in std_logic;
Q : out std_logic_vector (3 downto 0));
end CMP4BITS;
architecture DESCRIPTION of CMP4BITS is
signal Q_BUS_INTERNE : std_logic_vector(3 downto 0));
begin
process (CLOCK)
begin
if (CLOCK ='1' and CLOCK'event) then
Q_BUS_INTERNE <= Q_BUS_INTERNE + 1;
end if;
end process;
Q <= Q_BUS_INTERNE; -- affectation du bus interne au
-- signal de sortie Q
end DESCRIPTION;
35
Library ieee;
Use ieee.std_logic_1164.all;
Bascule T
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity BASCULET is
T comme TOGGLE ( basculement)
port (
La sortie change dtat chaque front
D,CLK : in std_logic;
( utilisation pour la synthse des
S : buffer std_logic);
compteurs)
end BASCULET;
architecture DESCRIPTION of BASCULET is
begin
PRO_BASCULET : process (CLK)
Begin
if (CLK'event and CLK='1') then
if (D=1) then
S <= not (S);
end if;
end if;
end process PRO_BASCULET;
end DESCRIPTION;
Compteur de
GRAY
Code binaire
rflchi
(codeur de
position par
exemple)
COMPTEUR GRAY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
entity GRAY is
port (H,R :in std_logic;
Q :out std_logic_vector(2 downto 0));
end GRAY;
architecture ARCH_GRAY of GRAY is
signal X :std_logic_vector(2 downto 0);
begin
process(H,R)
begin
if R='1' then X <= "000";
elsif (H'event and H='1') then
if X = "000" then X <= "001";
elsif X = "001" then X <= "011";
elsif X = "011" then X <= "010";
elsif X = "010" then X <= "110";
elsif X = "110" then X <= "111";
elsif X = "111" then X <= "101";
elsif X = "101" then X <= "100";
elsif X = "100" then X <= "000";
end if;
end if;
end process;
Q <= X;
end ARCH_GRAY;
36
instructions ;
.
instructions ;
instructions ;
instructions ;
37
38
39
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
entity DECAL_DG is
port (H,R,SENS :in std_logic;
IN_OUT,OUT_IN :inout std_logic);
end DECAL_DG;
architecture ARCH_DECAL_DG of DECAL_DG is
signal Q :std_logic_vector(3 downto 0);
begin
process(H,R)
begin
if R='1' then Q <= "0000";
elsif (H'event and H='1') then
if SENS = '1' then
Q <= Q(2 downto 0) & IN_OUT;
else Q <= OUT_IN & Q(3 downto 1);
end if;
end if;
end process;
OUT_IN <= Q(3) when SENS = '1' else 'Z';
IN_OUT <= Q(0) when SENS = '0' else 'Z';
end ARCH_DECAL_DG;
40
41
42
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
entity COMPTCAS is
port (H,R,EN :in std_logic;
CO :out std_logic;
Q :out std_logic_vector(3 downto 0));
end COMPTCAS;
architecture ARCH_COMPTCAS of COMPTCAS is
signal X :std_logic_vector(3 downto 0);
begin
process(H,R)
begin
if R='1' then X <= "0000";
elsif (H'event and H='1') then
if EN = '1' then X <= X + 1;
else X <= X;
end if;
end if;
end process;
Q <= X;
CO <= '1' when Q = 15 else '0';
end ARCH_COMPTCAS;
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44
Bibliographie
Certaines illustrations et exemples proviennent de cours ou douvrages
prsents ci-dessous
Introduction la Synthse logique Philippe LECARDONNEL & Philippe
LETENNEUR
Le langage de description VHDL T. BLOTIN
VHDl J.maillefert
Circuit Design with VHDL Volnei A. Pedroni
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