Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 1

Design Procedure for TwoStage CMOS Operational

Amplifier using 0.35 um
CMOS Technology
Advisor : Cheng-Ta Chiang., Ph. D
Reporter: Asih Setiarini

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 2

Outline

Introduction
Design Plan
Simulation Result
Conclusion
Q&A

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 3

Introduction
The advantages of two-stage operational
amplifier : simple structure and robustness
The parameters must be taken into consideration
to design OP: GBW, SR,CMR, OSR, offset, and for
negative feedback connection-frequency
compensation is necessary.
Simple technique of FC is connecting Cc
Cc is important factor for determining the noise
and power consumption
Aim of this work make the size of Cc much
VLSI

Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 4

Design Plan
OP AMP Specification

Min

Max

Voltage
0
3
CL
10

Ao
80

Unity gain frequency (fu)

10

Phase Margin
60

Slew rate
10

VCMR
0.2
2
Vswing
0.5
2.5

Process Parameter TSMC 0.35 um CMOS

up
0.0112

un
0.0414

upCox
53.03

unCox
213.8

|Vtp|
0.747

Vtn
0.565

unit

V
pF
dB
MHz
0
degree
V/us
V
V

m2/(Vs)
m2/(Vs)
uA/V2
uA/V2
V
V
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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 5

Design Plan

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 6

Design Plan
The calculations of the
design plan were realized
in an Excel- Sheet,
providing very fast easier
for recalculating.

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 7

Simulation
Variable of transistor for simulation

M=
W/L
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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 8

Simulation
Ac Gain, PM, BW

SR, Settling time

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 9

Simulation Result
The comparison between basic two stage CMOS opamp and the twostage CMOS operational
amplifiers employing Miller capacitor in
conjunction with the common-gate two stage Opamp

Gain = 78.62
dB

PM = 180 128.9
= 51.10

By adjust the CL value, this 24.158

stage OP can obtain the phasefu =MHz
margin as the specification at CL
= 5 pF.
PM = 180 118.6 = 61.40
Basic 2-stage OP, Cc = 2pF, Cl = 10pF
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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 10

Simulation Result
Gain = 78.62
dB
PM = 180 106.6
= 75.40

By mounting the CG in
conjunction of Miller
Capacitance no effect
on AC gain value, even
increase the PM and
unity gain frequency

fu = 5.111
MHz

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 11

Simulation Result

Based on the aim of this work, to design compensation

capacitor (Cc) much smaller with PM at least 60 0. Choose Cc
= 1.1 pF with CL = 5 pF.
Gain =
78.62 dB
PM = 180-117.5 =
62.50

fu = 8.565
MHz

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 12

Simulation Result
SLEW RATE
(+)
Slew rate is the maximum
rate of change of output
voltage per unit time.
(dVo/dt) The slope of the
output signal is the slew
rate.
SR (+) =
9.38
V/us

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 13

Simulation Result
SLEW RATE
(-)

SR (-) =
6.61V/u
s

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 14

Simulation Result
CMRR

CMRR = 78.0 dB at low

frequency range
Common Mode
Rejection ratio is
the ratio between
differential gain
and common mode
gain.
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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 15

Simulation Result
OFFSET

Offset = 1.50081
1.5
=0.0081 = 8.1 mV

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 16

Simulation Result
ICMR
ICMR=0 1.979 V

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 17

Simulation Result
OSR

OSR (-) = 80.61

mV
OSR (+) = 2.903 V

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 18

Simulation Result
Settling
Time

Settling tine
=307.3 ns

The time required by

the output to go from
10% to 90% of its final
value is called the rise
time.

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 19

Simulation Result
PSRR

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 20

Simulation Result
Design Procedure

Expected Result

Simulation result
(Cc=1.1pF, CL =
5pF)

Av (dB)

80

78.62

Fu (MHz)

10

8.565

Phase Margin (deg) 60

62.5

SR (V/us)

10/-10

9.38/-6.61

CMR (V)

0.2/2

0/1.98

Output Swing (V)

0.5/2

0.08/2.93

Power consumption 396 u

(W)

282 u

CMRR (dB)

78.0 at low
frequency

Settling time

307.3 ns

PSRR dB)

106 at low
frequency

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 21

Conclusion
The two-stage CMOS operational
amplifiers employing Miller capacitor
in conjunction with the common-gate
two stage Op amp :
Increase : bandwidth, phase margin
Decrease : size of Cc, power
consumption.

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 22

Reference
[1] J. Mahattanakul and J. Chutichatuporn,Design procedure for
two-stage CMOS opamp with flexible noise-power balancing
scheme,IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.
52, no. 8, pp. 15081514, Aug. 2005

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Department of Electrical Engineering ,

Faculty of Science and Engineering , NCYU

Slide No. 23

Thank
you

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