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Evaluation of an I.C:
Design principles
Hierarchy
Regularity
Modularity
Locality
Hierarchy
Divide and conquer
Divide in modules and repeating untill
each submodule is comprehensible
prebuilt component available
Virtual components IP
Regularity
Similar submodules
All level of design hierarchy: equal size
transistors, standard cell type library,
parameterized RAM, etc.
Design reuse
Modularity
Well defined functions and interfaces
Interaction with other modules well characterized
Behavioral, structural and physical interfaces
(function, signals, electrical and timing
constraints)
Locality
Well characterized interfaces for the
modulecorrespond to reduce global
variables in HDL
Advantage for the clock
Design methods
Microprocessor/DSP
Programmable logic
Gate Array and Sea of Gates
Cell-based
Full custom
Platform-based design (SoC)
Programmable logic
Chips with Programmable logic structure
Chips with Programmable interconnects
Chips with Programmable gate arrays
PAL
Inputs
(logic variables)
Logic gates
and
programmable
switches
Outputs
(logic functions)
Use to implement
circuits in SOP form
The connections in
the AND plane are
programmable
The connections in
the OR plane are
programmable
xn
Input buffers
and
inverters
x1 x1
xn xn
P1
AND plane
Pk
OR plane
f1
fm
x2
x3
Programmable
connections
f1 = x1x2+x1x3'+x1'x2'x3
P1
OR plane
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
AND plane
f1
f2
x1
x2
x3
f2 = x1'x2'+x1x2x3
P2
f1
P3
P4
AND plane
f2
Limitations of PLAs
PLAs come in various sizes
Typical size is 16 inputs, 32 product terms, 8 outputs
Each AND gate has large fan-in this limits the number of inputs that can be
provided in a PLA
16 inputs 316 = possible input combinations; only 32 permitted (since 32
AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates as well
This makes PLAs slower and slightly more expensive than some
alternatives to be discussed shortly
8 outputs could have shared minterms, but not required
Macrocell
Select
0
1
Flip-flop
Clock
Enable
f1
Macrocell Functions
Enable = 0 can be used to allow the output pin for f 1 to be used as an
additional input pin to the PAL
Select
0
1
D Q
Clock
Enable
f1
B
Sel = 0
En = 0
D Q
Sel = 0
Clock
0
1
En = 1
D Q
Select
Clock
0
1
D Q
Clock
22V10
12 inputs
10 I/Os
Product terms 9 10 12 14 16 14 12 10 8
24 pins
AMD introduced the 22V10
Allowed register bypassing.
components
Register
4:1 MUX
Tristate buffer
2:1 MUX
22V1
0
PAL
Programming SPLDs
PLAs, PALs, and ROMs are also called SPLDs Simple Programmable
Logic Devices
SPLDs must be programmed so that the switches are in the correct places
CAD tools are usually used to do this
A fuse map is created by the CAD tool and then that map is downloaded to the device via a
special programming unit
Fusible links
PROM
fusible-link MROM
custom programmed
by user
OTP (One Time
Programmable)
properties: Once
programmed, it
cannot be erase.
The SPLD is removed from the PCB, placed into the unit and
programmed there
PROM-Type Array
Full-PLA Array
16L8
PAL
Counter
design in
16R4 PAL
Sea of Gates
Cell-based
SSI
Memory
System level modules (processors, serial
interfaces, etc.
Mixed signal modules
Possible automatic generation of MSI modules
Option for power (1X, 2X, 4X.) and inputs
Full custom
Symbolic layout (old place transistors, wires,
contacts with graphic editor)
Silicon compilation: HDL that give all the views
of a project, i.e. behavior, timing, logical
Placement in a standard cell layout
Design Flows
From behavioral specifications
to layout
Front end till RTL synthesis
Back end from structural
specifications to Physical synthesis
and layout
Fig. 8.41
Design Economics
Stotal=Ctotal/(1-m)
Stotal : Selling price
Total cost
Non-recurring engineering costs
Recurring engineering costs
Fixed costs
NREs - Prototyping
Mask cost
Test fixture cost
Package tooling
Values:
Mask set for 130 nm about $500-1000
Test fixture $ 1000-50.000
Recurring costs
Cost of single IC after the development phase
Rtotal=Rprocess+Rpackage+Rtest
Rprocess=W/(NxYwxYpa)
W = wafer cost (500-3000 $)
N=Number die
Yw=Die yield (70-90 %)
=Packaging yield (95-99%)
Fixed costs
Data sheets
Application notes
Marketing and commercial costs
In 1970, Texas Instruments developed a maskprogrammable IC based on the IBM read-only associative
memory or ROAM. This device, the TMS2000, was
programmed by altering the metal layer during the
production of the IC. The TMS2000 had up to 17 inputs
and 18 outputs with 8 JK flip flop for memory. TI coined
the term Programmable Logic Array for this device.[2]
A programmable logic array (PLA) has a programmable
AND gate array, which links to a programmable OR gate
array, which can then be conditionally complemented to
produce an output.