Académique Documents
Professionnel Documents
Culture Documents
of
Low Power SoCs
Power Vs Energy
For battery operated devices, the distinction between power and energy is critical
Power
Time
Energy determines the life of a battery
Example :
Battery Capacity
=
Rated output voltage =
Average power
=
Standby time
=
=
1.7 Ah
3.7 V
0.5 W
1.7 * 3.7 / 0.5
12.58 hours
Energy
Batteries have finite amounts of energy stored in
them
Voltage
Reduce
Reduce
Running fast and then idling wastes energy
Voltage
Voltage
Reduce
Reduce
Voltage
Voltage
Reduce
Reduce
Voltage
Voltage
Energy
Energy
Saved
Energy
Run
RunTask
Task in
in
Available
Time
Available Time
Run
Run Task
Task Slow
Slow
as
Possible
as Possible
Time
Task 1
Idle
Task 2
Task 3
Only
Onlyneed
needto
torun
runjust
justfast
fastenough
enoughto
tomeet
meetthe
theapplication
applicationdeadlines
deadlines
Components of
Power
Power
Static
Dynamic
Switching
ISUB
ISUB
IGATE
IGIDL
IREV
IGATE
=
=
=
=
IGIDL
IREV
Sub-threshold leakage
Gate leakage
Gate Induced Drain Leakage
Reverse bias junction leakage
Internal
ICROWBAR
ICHARGING
A UPF Example
Power Domain
Power States
Controlled by Switches
Memories may require
Retention
States may require
sequencing info
States will effect
simulation
Level shifters
Isolation logic
Gas Stations
alternate supply
Identify elements
Manage
Implement
Analyze
Reuse
RTL
RTL
Soft IP
Constraint
Constraint
UPF
UPF
IP Configuration
RTL
RTL
Constraint
Constraint
UPF
UPF
Golden Source
Configuration
Configuration
UPF
UPF
IP Implementation
RTL
RTL
Constrnt
ConstrntUPF
UPF
Confign
ConfignUPF
UPF
+
Impltion
ImpltionUPF
UPF
IP Provider:
Synthesis
Impltion
ImpltionUPF
UPF
Creates IP source
Creates low power
implementation
constraints
Netlist
Netlist
IP Licensee/User:
P&R
Impltion
ImpltionUPF
UPF
Netlist
Netlist
Simulation, Logical
LogicalEquivalence
Equivalence Checking,
Checking,
Simulation,
Power domain
Level
shifter
Retention
Other
Elements
u1
u2
create_supply_port
create_supply_port
create_supply_port
create_supply_port
VDD
-domain top
VDD_SUB1 -domain top
GND
-domain top
VDD_SUB2 -domain top
Level shifter
considerations
Pick a power domain
or a set of elements
Select input ports,
output ports, or both
Tolerate a voltage
difference threshold
UP shift or down SHIFT
rule
Location (self, parent,
sibling, fanout, auto)
Insert or not insert
set_level_shifter SUB1_to_TOP \
-domain SUB1 \
-applies_to outputs \
-rule low_to_high \
-location parent
set_level_shifter TOP_to_SUB1 \
-domain SUB1 \
-applies_to inputs \
-rule high_to_low \
-location self
set_level_shifter SUB2_to_TOP \
-domain SUB2 \
-applies_to outputs \
-rule low_to_high \
-location parent
set_level_shifter TOP_to_SUB2 \
-domain SUB2 \
-applies_to inputs \
-rule high_to_low \
-location self
Domain1
constant
PM ctrl
logic
VDD
GND
set_isolation_control ISO_STRAT \
-domain SUB0 \
-isolation_signal reg_out[25] \
-isolation_sense high \
-location parent
Domain1
constant
PM ctrl
logic
VDD
GND
set_retention_control key_desIn \
-domain SUB0 \
-save_signal {key_b_r_reg[16][27]/pin:Q high} \
-restore_signal {key_b_r_reg[16][26]/pin:Q low}
PM ctrl
logic
VDD
GND
create_power_switch SUB0_SW \
-domain SUB0 \
-input_supply_port {TVDD VDD} \
-output_supply_port {VDD VDD_SUB0_SW} \
-control_port
{NSLEEPIN1 SE_ME_on_1 } \
-control_port
{NSLEEPIN2 SE_ME_on_2 } \
-ack_port
{NSLEEPOUT1 SE_ME_on_ack_1}
\
-ack_port
{NSLEEPOUT2 SE_ME_on_ack_2}
\
-on_state {SW_on TVDD {NSLEEPIN2 &
NSLEEPIN1} } \
-off_state {SW_off {!NSLEEPIN2 & !NSLEEPIN1}}
VDD
TVDD
NSLEEPIN1
NSLEEPOUT1
NSLEEPIN2
NSLEEPINOUT2
VDD
VDD_SUB0_SW
PM ctrl
logic
VDD
GND
Domain1
constant
PM ctrl
logic
VDD
GND
SUB2_H}
SUB2_L}
VDD
VDD_SUB0_S
W
VDD_SUB
1
VDD_SUB
2
pst0
VDD_N
SW_on
SUB1_H
SUB1_H
ps1
VDD_N
SW_off
SUB1_L
SUB1_L
add_power_state object_name
-state state_name
-supply_expr {boolean_expr}
-logic_expr {boolean_expr}
[-simstate simstate]
-legal | -illegal
-update
Legality
G1
G2
B1
B2
B3
M1
M2
Green
mod
Blue
Use Components in an
Design
G1 G2 B1 B2 B3 M1 M2
G1 G2 B1 B2 B3 M1 M2
Green
Green
mod
Blue
G1 G2 B1 B2 B3 M1 M2
Green
mod
Blue
mod
Blue
Functional specification
Checking the specification
Corruption recognized
Srikanth will provide more detail
Structural specification
Correlation to structural
No new corruption
Verification of Power
Managed Designs
Range of Voltage-Control
Techniques
1.2V
1.2V
1.0V
1.0V
1.2V
OFF
1.2V
0.9V
0.9V
Multi-Vdd (MV)
PWR
PWR
CTRL
CTRL
1.0V
1.0V
0.9V
0.9V
0.9-1.2V
0.9-1.2V
VDDB
A
1.0V
1.0V
1.2V
RET
1.2V
0.9V
0.9V
1.2V
0.6V
1.2V
0.9V
0.9V
VSSB
Dynamic or Adaptive
Voltage Frequency Scaling
(DVS, DVFS, AVS, AVFS)
1.0V
1.0V
Variable VTH
(Back Bias P/N)
1.0V
1.0V
0.9V
0.9V
Low-VDD Standby
Display
Display
in in
Display in
OFF Mode
Normal
HP Mode
Standby
Mode with
Power Switches
CPU in
CPU in
Normal
Standby
HP
Mode
Mode
Tx/Rx
Tx/Rx in
in
Normal
Standby
Mode
Level Shifters
Isolation Cells
V2
V3
Audio in
OFF Mode
Audio
in
with
Normal
Power
Mode
Switches
PMU
Video in
Video
OFFinMode
Normal
with
Mode
Power Switches
Correct
Multiple
implementation
power
states,
of transitions
LP specific
and
design
Verification
must now
understand
voltage
elements
must
mustbe
happen
verifiedStandby
values
Phone Call sequences
PDA
Bug Classification
Structural Errors
Missing Isolation, Level Shifters
Devices in wrong domains
Wrong Rail connections
Control Errors
Mistimed Control signals
Incorrect control activation sequence
Incorrect gating/ungating in off/low power
states
Architectural Errors
Incorrect partitions, policies
Structural Errors
PMIC/PMU
ISO-Enable
Domain 1
ON(1.2V)/OFF
Domain 2
0.9-1.2
Isolation
Domain 3
ON (1.2V)
Level Shifters
Incorrect Isolation
Sequence
Control Error
Intended
Intended
Behavior
Behavior
1.
1.Gate
Gatethe
theclk
clk
2.
2.Assert
Assertiso
isoto
to
00
3.
Assert
sleep
3.
Assert
sleep
Actual
Behavior
Actual
Behavior
to
to00
1.
1.Gate
Gatethe
theclk
clk
2.
2.Assert
Assertsleep
sleep
to
to00
3.
3.Assert
Assertiso
isoto
to
00
X is observed due
to incorrect iso timing
Registers initialized to X
after power restoration
Control signal
sequence error is
discovered due to X
propagation
A[63:0]
1.1V
0.8V
Island 2
1.2V
1.1V
0.9V
0.8V
1.2V
1.1V
0.9V
0.8V
Need Level
Shifter
Voltage-Aware Simulation is
now necessary!
0.7 V
1
1.0 V
1
0.7 V
1
1.0 V
1
Voltage-Aware Simulators
are Electrically Accurate
Modeling
True Voltage Aware
Simulation
Parameterized
Parameterized source
source
code
code provided
provided
Real
Real Voltage
Voltage
Voltage
Voltage Ramp
Ramp
Retention stretches
language
semantics
Retention : A balloon latch is used to retain state when power is
turned off
Need to
simulate and
verify this!
negedge reset_n or
posedge save or
posedge restore)
if (!vdd)
q
<=
1bx;
else if (!reset_n) q
<= 0;
else if (save)
q_s <= q;
else if (restore) q
<= q_s;
else
q
<= d;
Verifying Retention
Complete power Sequence
CLK
CLK -EN
Enable
Clock
Disable
Clock
SAVE
ISO
PWR EN
VDD
PWR RDY
RESTORE
Save
Enable
Isolation
Disable
Power
Ramp
Voltage
Disable
Ready
Disable
Isolation
Enable
Power
Ramp
Voltage
Enable
Ready
Restore
Verifying Retention
Corner Cases Can Be Tricky
PWR GATED DMA
PREMATURE
RESTORE SIGNAL
SAVE
ACTUAL
RESTORE
REG A
aa
EXPECTED
RESTORE
REG B
bb
bb
Coding Guidelines
1b0 and 1b1 no single supply1 or supply0
Use tie_hi_<name> or tie_lo_<name>
Redefining Coverage
CORE (ON)
LP0
LP1
AllOn
LP2
AllOff
AllOn
CORE
AllOn
DOMAIN
DOMAIN11
DOMAIN
DOMAIN22
ON/OFF
ON/OFF
ON/OFF
ON/OFF
CORE
Domain1
Domain2
AllOff
OFF
OFF
OFF
LP0
ON
OFF
OFF
LP1
ON
OFF
ON
LP2
ON
ON
OFF
AllOn
ON
ON
ON
ON
PS_ENABLE
PMU
Absence of one
leaf-level assertion
will cause failure of
design
Source Assertion:
When PS_ENABLE =1,
ISO_ENABLE = 0
Source level
assertions cannot
be relied upon to
ensure correct
operation of design
ISO_ENABLE
RTL
Lines
6099
Voltage Power
Islands States
4
RTL
Assertions
Gate Level
Assertions
685
1891
Slide 79 (of 118)
Successive Refinement
Example
1.
UPF Constraints
2.
UPF Configuration
3.
UPF Implementation
nPWR
WAKE- UP REQ
SLEEP REQ
VDD_SW
CLOCK ACK
( CLAMP _ACK)
(N _ RETAIN _ACK)
Power -Gated
Region PD
CLOCK
ENABLE
(N _ RESET _ACK)
N_ START _ACK
nRESET
N_ PWR_ACK
nCLAMP
S
y
n
c
h
r
o
n
i
z
e
r
s
CLOCK _REQ
Power Gating
Controller
State Machine
CLAMP _REQ
N _RETAIN_REQ
N _ RESET _REQ
N _ START _REQ
N_ PWR_REQ
SYSTEM CLOCK
VSS
Can use UPF inferred clamps to stop clocks and assert reset
Needs care to avoid timing issues
CLOCK
N_CLAMP
SAVE
RESTORE
N_RESET
N_PWR
1.
2.
3.
4.
5.
Apply power
Remove reset
Optionally restore state
Remove isolation
Start the clocks
Top
A1
B1
A2
B2
B3
B4
Conclusion:
References
Accellera
http://www.lpmm-book.org
Thank You!