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MANIACS
Sdn Based
Hardware accelerated
FIREWALL
By
Net Maniacs
AbhishekKatuluru
ArunKumarLokre
MohdYusuf Abdul Hamid
VasanthamSudheer Kumar
SantoshKalakonda
NET MANIACS
Problem statement
30000
00
Infected
Hosts
3000
0
100Mbp
s
3000
LOSS
00$1.2
BILLION
1Gbp
s
10
Gbps
Problem statement
Performance
Evaluation
Hosts
Affect
ed
ANALYSI
S
Hardware Update time
2us
Firmware Update time
50us
Hardware
Firmware
1666.5
166.65
16.65
0.666
100Mb
ps
66
6.6
1Gbps
Line Rate
10
Gbps
NET MANIACS
CONTR
OL
REROUT
UPDATE
ALLOW
DROP
D
E! !
NETFPG
A
NODE 1
NODE 2
NODE 3
NET MANIACS
PROJECT ARCHITECTURE
OUTPUT PORT LOOKUP
INSTRUCTION
PACKET
ARBITER
FIF
O
LOOKUP
HARDWAR
E
CPU
CPU
UPDAT
ED
REROUTE
HW
ACC
FIF
O
REROUTE
HW
ACC
ARBITER
OUTPUT QUEUE
CPU
CPU
NET MANIACS
Cpu architecture
Threa
d1
Instruct
T1:
ion
ADD
SW
Memory
Bran
ch
Logic
ID/EX
Regist
er File
ALU
ALU
Instruct
T2:
ion
ADD
LW
Memory
Threa
d2
Regist
er File
Bran
ch
Logic
MEM
Data
Memor
y
Memor
y
Mappe
d for
HW
Acc
WB
M
U
X
NET MANIACS
Fifo design
CONVENTIONAL
MEMORY
DESIGN
FIFO
BUSY
PACKE
T
RECEIV
ED
(Accept
Current
Pkt and
Send
Previous
Pkt)
CPU
BUSY
(CPU
Processin
g)
0
Rd_Ptr
Wr_Ptr
STAR
FIFO
T
Memory
FIFO
PACKET
PROCES
SED
Up to
50%
255
SEND
256
PKT
CONVENTIO
NAL STATE
MACHINE
Scratch
Memory
511
PROC
Memory
ESS
Mapped
I/O
PKT
FIFO
BUSY
NET MANIACS
IP LOOKUP
IP
Par
Pack se
Pack
et Log
et
ic
ACTIO
ACTIO
N
N
IP
Allow
Allow
ed
ed
List
List
Deni
Deni
ed
ed
List
List
Matc
h
MATCH
MATCH Normal/
ER
Inst Pkt
ER
Match
CAM
CAM
en
CAM
CAM
en
Matc
h
Performance comparison
NET MANIACS
Project schedule
NET MANIACS
Description
Completion Date
Phase 1
Multi-Core Processor
April 7 2014
Phase 2
April 14 2014
Phase 3
April 28 2014
Phase 4
In Progress
Phase 5
In Progress
NET MANIACS