DSP

Execution control

Hardware Support for fast looping

Zero overhead looping
All loop operations done in hardware
Fast interrupts for I/O handling
Real time constraints
Stream processing : processor completes the
operation within the sampling period itself
- Block processing
Debugging support.

Specialized Peripherals

Synchronous Serial port

Parallel ports
Bit I/O ports
Timers
On-chip A/D,D/A convertors
On-chip DMA controller

DSP Processors
TI 5X family
TI 6X family
SHARC

C5X Family

Fixed point processor

Modified Harvard Architecture
1 program memory bus
3 data memory bus
40 bit ALU
Multiple implementations
1 , 2 instructions / cycle

Sample configurations
C5409

C5510

1. 100 MIPS @100 MHZ

400 MIPS @200 mhz

2. Address space size

- Data 64k words
- Program 8M words

Total address space

-8M words

3. On board memory
- RAM 16K words
- ROM 32 K words

On board memory
- RAM 160K words
- ROM 16k Words

4. Three buffered serial ports

Three McBSP serial ports

5. One timers

Two timers

TI C54x Architectural
features
40 bit ALU+ barrel Shifter
Multiple internal buses: 1
Instructions, 3 Data, 4 address.
17* 17 multiplier
Single cycle exponent encoder
Two address generator with
dedicated register
CSSU unit

ALU
40 bit ALU performs 2s complement
arithmetic & logical functions
ALU supports two 16 bit operations in one
cycle
Supports saturation & sign extension
17 * 17 bit hardware multiplier coupled with
a 40 bit adder is linked to accumulator to
form MAC unit
o/p of adder is passed through a unit that
detects a zero & an over flow.

ALU Architecture

Instruction set features

repeat & block repeat instructions
Instructions that need 2,3 operands
simultaneously
Conditional store
Fast return from interrupt

Some C54x Register

Circular buffer size register

Block repeat registers
Interrupt register
Processor mode status register

Pipeline processor
Program pre-fetch
Fetch: load instruction from program
bus to IR
Decode
Access
Read
Execute

C54x Power down modes

Three IDLE instructions
IDLE1: shuts down CPU
IDLE2: Shuts down CPU & on chip
peripherals
IDLE3: Shuts down chip completely

C54x buses

PB: program read bus

CB, DB : data read bus
EB : data write bus
PAB, CAB, DAB, EAB : address bus
Can generate two data memory
address per cycle.

Buses & access

PAB
Progra
m read

Progra
m
Write

CAB

DAB

EAB

PB

CB

DB

EB

*
*

Data
Single
read

Data
Dual
read

Data
Long
read

*
(hi)

*
(lo)

*
(hi)

*
(lo)

TMS320C55x
Power efficient DSP for personal &
portable applications
High performance through increased
parallelism
More built in instructions and user
programmable parallel functions
Automatic power management for all
peripherals, memory arrays & CPUs

55x Architecture
Provides dual MAC units each capable of
17*17 multiplication & 40 unit addition &
subtraction with optional saturation in cycle.
40 bit ALU with additional 16 bit ALU for
optimizing parallel operations
Compare, select & store unit
4 general purpose 40 bit accumulator
Supports 12 internal buses to perform up to 3
data reads & two data writes in single cycle.

Architecture overview
CPU uses software stacks that supports
16 bit and 32 bit push & pop
Supports variable length instructions for
improving code density
CPU consists of 4 functional block
- IU
- PU
- AU
- DU