Interrupt

Chapter 10

The AVR microcontroller

and embedded
systems
using assembly and c

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Polling Vs. Interrupt

Polling

Ties down the CPU

Interrupt

while (true)
{
if(PIND.2 == 0)
//do something;
}

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

Efficient CPU use

Has priority
Can be masked

main( )
{
Do your common task
}
whenever PIND.2 is 0 then
do something

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Interrupt unit

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Steps in executing an interrupt

PB0

PB1

(INT2) PB2

(OC0/AIN0)
PB3
(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

0002

ATmega3
2
PC
:

0016
0015
0014
0013
0012
000D
0009
000A
000B
000C
0006
0008
000F
0004
000E
0007
0005
0000

40

VCC

39

PA0 (ADC0)

38

PA1 (ADC1)

37

PA2 (ADC2)

36

PA3 (ADC3)

35

PA4 (ADC4)

34

PA5 (ADC5)

33

PA6 (ADC6)

32

PA7 (ADC7)

VCC

10

31

AGND

GND

11

30

AVCC

XTAL2

12

29

PC7 (TOSC2)

XTAL1

13

28

PC6 (TOSC1)

(RXD) PD0

14

27

PC5 (TDI)

(TXD) PD1

15

26

PC4 (TDO)

(INT0) PD2

16

25

PC3 (TMS)

(INT1) PD3

17

24

PC2 (TCK)

(OC1B) PD4

18

23

PC1 (SDA)

(OC1A) PD5

19

22

PC0 (SCL)

(ICP) PD6

20

21

PD7 (OC2)

S
P
Stac
k

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

Addres Code
s
.INCLUDE "M32DEF.INC"
.ORG 0
;location for reset
0000
JMP
MAIN
.ORG 0x02 ;location for external INT0
JMP
EX0_ISR
0002 MAIN: LDI R20,HIGH(RAMEND)
OUT
SPH,R20
0002
LDI
R20,LOW(RAMEND)
OUT
SPL,R20
0004
SBI
DDRC,3
;PC.3 = output
0005
SBI
PORTD,2
;pull-up
0006
activated
0007
LDI
R20,1<<INT0 ;Enable INT0
0008
OUT
GICR,R20
0009
SEI
;Set I (Enable
Interrupts)
000A
LDI
R30, 3
000F
000B
LDI
R31, 4
000C
ADD
R30, R31
000D
000E HERE:JMP HERE
000F
0010 EX0_ISR:IN R21,PORTC
LDI
R22,0x08
EOR
R21,R22
OUT
PORTC,R21
0012
RETI
0013
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0014
UpperSaddleRiver,NJ07458.AllRightsReserved.
0015

Edge trigger Vs. Level trigger in external

interrupts

LDI
OUT

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

R20,0x02
;falling
MCUCR,R20

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Edge trigger Vs. Level trigger

(Cont.)

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Interrupt priority
Highest
priority

Lowest
priority
AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Interrupt inside an interrupt

The I flag is cleared when the AVR

begins to execute an ISR. So,
interrupts are disabled.
The I flag is set when RETI is
executed.

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.

Task switching and resource

conflict

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Does the following program work?

.INCLUDE "M32DEF.INC"
.ORG
0x0
;location for reset
JMP
MAIN
.ORG
0x14
;Timer0 compare match
JMP
T0_CM_ISR
;---------main program-----------------------------.ORG
0x100
MAIN:
LDI
R20,HIGH(RAMEND)
OUT
SPH,R20
LDI
R20,LOW(RAMEND)
OUT
SPL,R20 ;set up stack
SBI
DDRB,5 ;PB5 = output
LDI
R20,160
OUT
OCR0,R20
LDI
R20,0x09
OUT
TCCR0,R20
AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

17
LDI
R20,(1<<OCIE0)
18
OUT
TIMSK,R20
19
SEI
20
LDI
R20,0xFF
21
OUT
DDRC,R20
22
OUT
DDRD,R20
23
LDI
R20, 0
24 HERE: OUT
PORTC,R20
25
INC
R20
26
JMP
HERE
27 ;--------------------------ISR for Timer0
28 T0_CM_ISR:
29
IN
R20,PIND
30
INC
R20
31
OUT
PORTD,R20
32
RETI
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Saving SREG

We should save SREG, when we

change flags in the ISR.
PUSH
IN
PUSH
...
POP
OUT
POP

AVRMicrocontrollerandEmbeddedSystemUsingAssemblyandC
Mazidi,Naimi,andNaimi

R20
R20,SREG
R20
R20
SREG,R20
R20

2011PearsonHigherEducation,
UpperSaddleRiver,NJ07458.AllRightsReserved.