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Lec 12
Dynamic Logic Circuits
Goals
Understand
Pass-Transistor Latch
Circuit and Operation
Soft note
D
MP
ML Q
Vx
Cx
MD
CK
Operation
CK = H, D=H or L : CX is charged up or down through MP, and X
becomes H or L (depends on D input) since MP is on D and X
are connected.
CK = L: X is unchanged since MP is off and CX is isolated from D,
and the charge is stored on capacitances CX.
For X = H, Q = L and Q = H
For X = L, Q = H and Q = L
Pass-Transistor Latch
Soft Node Concept
During CK = 1: Let D = 1, i.e. VD = VOH = VDD MP is conducting
and charges CX to a weak 1 (VX = VDD VTD) Q = L (VQ<VTD)
and Q = H(VQ=VDD).
During CK = 0: Logic-level VX is preserved through charge
storage on CX. However, VX starts to drop due to leakage.
What value does VX have to deteriorate to no longer like a stored ?
Example (see p359~359, Kang and Leblebici): For an inverter
with VDD = 5V, VT,n = 0.8V , VOL = 2.9V and VIH = 2.9V, initial VX
=4.2 V. But due to leakage currents, this will decline over time.
When it declines below VIH(2.9V), then a logic 0 out of the
inverter can no longer guaranteed.
Thus, to avoid an erroneous output, the charge stored in CX must
be restored or refreshed to its original level before VX declines
below 2.9 V.
MP
Vx
X
Cx
CK
Vin=VDD D
S
MP
ID
Vx
X
Cx
CK
V DD V X V T ,MP
CX
dt
2
Note that the VT,MP is subject to substrate bias effect and therefore,
depends on the voltage level VX. We will neglect the substrate bias
effect for simplicity.
7
2
0
k n 0 V DD V X V T ,MP
VX
Therefore,
1
2C X
k n V DD V X V T ,MP 0
1
1
2C X
k n V DD V X V T ,MP V DD V T ,MP
and,
k n V DD V T ,MP t
2C X
V X (t ) V DD V T ,MP
1 k n V DD V T ,MP t
2C X
CMOS Digital Integrated Circuits
Vmax
Vmax=VDD-VT,MP
t
0
VX rises from 0V and approaches a limit value Vmax = VX(t)|t= = VDDVT,MP, but it can not exceed this value, since the pass transistor will turn
off at this point (VGS=VT,MP). Therefore, it transfers a weak logic 1.
The actual Vmax by taking the body effect into account is,
V max V DD V T 0,MP
2 F V max 2 F
1
1
2C X
Soft note
MP
Vin
Vx
X
Cx
CK
Vin=0
D
MP
ID
Vx
X
Cx
CK
dV X k n
2 V DD V T ,MP V X V 2X
CX
dt
2
10
Note that the VSB=0. Hence, there is no body effect for MP (VT,MP=
VT0,MP). But the initial condition VX(t=0)=VDD VT,MP contains the
threshold voltage with body effect. To simplify the expressions,
we will use VT,MP in the following.
VX
2C X
dV X
dt
2
k n V DD V T , MP 2V DD V T ,MP V X V X
2V DD V T ,MP V X
CX
ln
k n V DD V T ,MP
VX
VX
V DD V T , MP
Therefore,
2V DD V T ,MP V X
C
X
t
ln
k n V DD V T , MP
VX
and,
V X (t )
11
2V DD V T ,MP
1 e
tk n V DD V T , MP / C X
CMOS Digital Integrated Circuits
t 90%
12
2 0.9 V DD V T ,MP
CX
ln
0.9
k n V DD V T ,MP
V DD V T ,MP
CX
ln 1.22
k n V DD V T ,MP
t10%
1.9
CX
ln
k n V DD V T ,MP 0.1
Vmax=VDD-VT,MP
MP
Ileakage Vx
Igate=0
Cx
CK=0
VCK=0
Ileakage
VX
Vin=0
n+
p-type Si
13
Isubthreshold
n+
CX
Ireverse
CMOS Digital Integrated Circuits
Ileakage VX
Vin=0
n+
Isubthreshold
Ireverse
p-type Si
Ileakage
Isubthreshold
CX
n+
Ireverse
Vx
Cj(VX)
Drain-substrate pn-junction
14
Isubthreshold is the subthreshold current for the pass transistor with CK=0.
Ireverse is the reverse current for the source/drain pn junction at node X
Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX
Cin: due to oxide-related parasitics, can be considered constants.
CMOS Digital Integrated Circuits
Ileakage
Vx
Cin= Cgb + Cpoly + Cmetal
Isubthreshold
Ireverse
Cj
Cin
CX= Cin + Cj
Drain-substrate pn-junction
The total charge stored in the soft node can be expressed as,
Q = Qj (VX) + Qin where Qin = CinVX
The total leakage current can be expressed as the time derivative
of the total soft-node charge Q
I leakage
dQ
dt
dQ j (V X )
dQin
dt
dt
dQ j (V X ) dV X
C in dV X
dt
dt
dV X
15
dQ j (V X )
dV X
C j (V X )
Therefore,
AC j 0
AC j 0 SW
1 V X
1 V X
0
0 SW
kT N D N A
ln
q ni2
0 SW
kT N D N ASW
ln
2
q
ni
I leakage
dV X
AC j 0
PC j 0 SW
C in
dt
1 V X
1 V X
0
0 SW
17
MP
M1
Cx
CK
soft node
3
1
MP 4
1
CK
diffusion
18
5
5
6
2
2
3
M1
4 1
metal polysilicon
CMOS Digital Integrated Circuits
1
MP 4
1
CK
2
2
3
M1
4 1
20
1 V X ,max
0 SW
4.56
6.0
4.71 fF
3.68
3.68
1
1
0.88
0.95
CMOS Digital Integrated Circuits
21
Voltage Bootstrapping
The Voltage bootstrapping is a technique to overcome the threshold
voltage drops of the output voltage levels in pass transistor gates or
enhancement-load inverters and logic gates.
Consider the following circuit with VXVDD M2 is in saturation. If
Vin is low, the maximum output voltage is limited as
Vout(max) = VX VT2(Vout)
VDD
Vx
M2
Vout
Vin
22
M1
Cout
M3
Vx
CS
M2
Cboot Vout
Vin
M1
Cout
C boot
V DD V OL
C S C boot
If Cboot >> CS, then for Vout rising to VDD,
VX(max) 2VDD VT3 VOL > VDD VT2.
for realistic values of the voltages. Thus, it is feasible to use the circuit to
obtain Vout =VDD.
.
24
V X V DD V T 3
V T 2 Vout VDD V T 3 VX
C boot
C S C boot
V DD V OL
V T 2 Vo utVDD V T 3 VX
C boot
C S V DD V OL V T 2 VoutVDD V T 3 VX
25
M2
Cboot
Vout
Vin
M1
A
B
Comb.
Logic
2
Comb.
Logic
3
F1
F2
1
2
t
phase1
phase2
1, 2 non-overlapping clocks
Logic levels are stored on input capacitances during the inactive clock
phase.
27
Vin
28
VDD
Cin1
Cout1
VDD
Cin2
Cout2
Vout
Cin3
Cout3
VDD
VDD
2
Vout
Vin
29
Cin1
Cout1
Cin2
Cout2
Cin3
Cout3
VDD
1
Z
A
B
C
nMOS
Logic
Stage 1
nMOS
Logic
Stage 2
30
1=H
2
Vout1
Vin
VDD
2=H
Cin2
Cin1
Cout1
Cout2
Vout3
Cin3
Vout2VOL
VDD
1
Vout1
Vin
VDD
Vout2
Cout1
Cin1
VDD
Cout3
VDD
Vout2
Cin2
Cout2
Vout1VOL
Vout3
Cin3
Cout3
Vout3VOL
VDD
VDD
VDD
Vout
Vin
32
Cin1
Cout1
Cin2
Cout2
Cin3
Cout3
VDD
2
Z
A
B
C
nMOS
Logic
Stage 1
nMOS
Logic
Stage 2
33
1=H
VDD
Vout1
Vin
Cin1
Cout1
Cin2
Cin1
Cout1
Vout10V
Vout3
Cin3
Cout2
Vout2
Cin2
Vout3
Cin3
Cout2
Vout2VOL
Cout3
Vout3VOL
VDD
Vout2 0V
VDD
1
Vout1
Vin
1
Vout2
Vout1VOL
VDD
2
2=H
VDD
Cout3
Vout30V
Va
Cout1
Cin2
Charge Sharing
2 = 0: Qout1 = Cout1Vb and Qin2 = Cin2Va
2 = 1: Qtotal = Cout1Vb + Cin2Va and Ctotal = Cout1 + Cin2
The resulting voltage across Ctotal is
VR = Qtotal / Ctotal = (Cout1Vb + Cin2Va )/ (Cout1 + Cin2)
If Vb = VDD and Va << Vb VR Cout1VDD /(Cout1 + Cin2)
VR VDD if Cin2 << Cout1
35
2
1
A
B
F1
Stage 1
Stage 2
1
1
36
2
CMOS Digital Integrated Circuits
soft node
VDD
CK
VX
Vin
CK
37
CX
Vout
Cy
CMOS Digital Integrated Circuits
CK
V1
V2
CK
38
CK
V3
CK
V4
CK
CMOS Digital Integrated Circuits
Mp
Vout
C
inputs
nMOS
Logic
Internal
capacitance
Me
Vout
=0 C precharges to
VDD (output is not available
during precharge)
=1 C selectively
discharges to 0 (output is
only available after
discharge is complete)
evaluate
precharge
precharge
t
t
39
Mp
Vout
A1
B1
A2
B2
A3
Me
Z is high when =0
Z=(A1 A2A3 +B1B2)
40
Advantages
Disadvantages
The available time of output is less than 50 % of the time.
Pull-down time is degraded due to series active switch to 0.
Logic output value can be degraded due to charge sharing with other gate
capacitances connected to the output.
Minimum clock rate determined by leakage on C.
Maximum clock rate determined by circuit delays.
Input can only change during the precharge phase. Inputs must be stable
during evaluation; otherwise an incorrect value on an input could
erroneously discharge the output node. (single phase P-E logic gates can
not be cascaded)
Outputs must be stored during precharge, if they are required during the
next evaluate phase.
41
VDD
Mp1
Vout1
inputs
1st stage
nMOS
Logic
Me1
Mp2
Vout2
2nd
1
Me2
precharge evaluate
Vout
Vout
t
Vout1 does not switch from
1 to 0 fast enough
t
correct state
erroneous state
t
Evaluate:
Me1, Me2 ON
Mp1, Me2 OFF
Problem: All stages must evaluate simultaneously one clock does
not permit pipelining of stages.
42
VDD
inputs
Vout
nMOS
Logic
precharge evaluate
1
t
43
=0
X precharges to VDD, and Vout = 0.
=1
X remains high, and Vout remains
low.
X discharges to 0, and Vout
changes from 0 to 1.
CMOS Digital Integrated Circuits
VDD
VDD
X1
inputs
X1
X2
X3
nMOS
Logic
evaluate
X2
nMOS
Logic
X3
nMOS
Logic
evaluate
precharge
teval
t
t
t
t
44
inputs
X1
nMOS
Logic
VDD
VDD
X3
X2
nMOS
Logic
nMOS
Logic
46
VDD
VX
Vout
C1
N
C2
VX = VDDC1/(C1+C2)
Keep C2 << C1
Assume that all inputs are low initially, and the voltage across C2=0V
During the precharge, C1 is charged to VDD
If transistor N switches from 0 to 1 during the evaluation phase, the
charge initially stored in C1 will be shared by C2. Therefore, the value of
VX will reduced.
47
VX
inputs
48
nMOS
Logic
Vout
VX1
nMOS
Logic
Vout1
C1
Vout2
VX2
nMOS
Logic
49
C2
VDD
VDD
VX1
VA
VB
VX2
Vout
C1
C2
Let C1 = C2 = 0.05pF. VX1 = 0, and VX2 = 0 at t=0
C4
P4
P3
P2
P1
G4
C3
G3
C2
G2
C1
G1
C0
51
C1=G1+P1C0
C2=G2+P2G1+P2P1C0
C3=G3+P3G2+P3P2G1+P3P2P1C0
C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0
Gi = Ai Bi
Pi = Ai Bi
CMOS Digital Integrated Circuits
Mp
Vout
CL
A
B
C
R0
D
Me
52
R1 1
0
C0
C1
CL
53
R1 1
VDD
nMOS
Logic
nMOS
Logic
pMOS
Logic
to nMOS stage
nMOS stage
precharge
pMOS stage
pre-discharge
VDD
all stages
evaluate
to pMOS stage
nMOS stage
precharge
pMOS stage
pre-discharge
all stages
evaluate
Advantages
An Inverter is not required at the output of stages
Allow pipelined system architecture
Disadvantages: Also suffer from charge sharing and leakage
54
VDD
VDD
55
56
VDD
VDD
VDD
nMOS
Logic
N-block
pMOS
Logic
to next N-block
P-block
Using tristate inverters between stages decouples the stages and enables pipelined operation
VDD
VDD
VDD
58
Summary
Full complementary static logic is best option in the majority of
CMOS circuits.
Noise-immunity is not sensitive to kn/kp
Does not involve precharge of nodes
Dissipate no DC power
Layout can be automated
Large fan-in gates lead to complex circuit structures (2N
transistors)
Larger parasitics
Slower and higher dynamic power dissipation than alternatives
No clock
59
Summary (Cont.)
Pseudo-nMOS static logic finds widest utility in large fan-in
NOR gates.
Require only N+1 transistors for N fan-in
Smaller parasitics
Faster and lower dynamic power dissipation than full CMOS
Noise immunity sensitive to kn/kp
Dissipate DC power when pulled down
Not well suited for automated layout
No clock
60
Summary (Cont.)
CMOS domino logic should be used for low-power, high speed
applications
Require only N+k transistors for N fan-in, size advantages of
pseudo-nMOS.
Dissipate no DC power
Noise immunity is not sensitive to kn/kp
Use of clocks enables synchronous operation
Rely on storage on soft node
Require exhaustive simulation at all the process corners to
insure proper operation
Some of the speed advantage over static gates is diminished by
the required per-charge (pre-discharge) time.
61