Computer Architecture & Organization

Architecture  attributes visible to the programmer

 Instruction set, number of bits used for data representation,
I/O mechanisms, addressing techniques, etc.
hmmm …
 e.g. Is there a multiply instruction?
chicken/egg
Organization  how features are implemented problem ?
 Control signals, interfaces, memory technology, etc.
 e.g. Is there a hardware multiply unit or is it done by
repeated addition?

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 1

 What Should I already know re
Computer Arch & Org ?
“Black Box” ! connected devices
communication Peripherals
links keyboard
mouse
network
telephone . . display
cable . . disk / optical
computer
wireless speakers
. .
other ? printer
other ?

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 2

 ITBB
Function & Structure
 SYSC 2001 will look inside the black box (ITBB)!
• peripherals and commn links are outside black box

Will construct various models of ITBB components:

 Function  the operation of individual components as
parts of the structure
 Structure  how components relate to each other

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 3

 IMPORTANT
Function SLIDE !

 ALL computer functions are:

• Data PROCESSING
• Data STORAGE Data = Information
• Data MOVEMENT
• CONTROL Coordinates How
Information is Used

 NOTHING ELSE!

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 4

 Functional view of Black Box
connections Operating Environment
to peripherals source/sink for information
and commn
links
MOVEMENT

ITBB
CONTROL

STORAGE PROCESSING

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 5

 Operations (1) Data movement

e.g. copy a file

between disks

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 6

 Operations (2) Storage

e.g. load a text

file for editing

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 7

 Operation (3) Processing from/to storage

e.g. compute an
intermediate
result from some
operands & save
for later use

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 8

 Operation (4)
Processing from storage to I/O

e.g. compute and

display a result
from some
operands

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 9

 Peripherals
Structure - Top Level ITBB More
Black
Computer Boxes
ITBB!
Input
Computer Output Central
Processing
Unit
Systems
Interconnection

Communication Main
lines Memory

What about
Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 10
 Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Drilling
Control Down
Unit
I(ITBB)!
What about
Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 11
 Too deep for Structure - The Control Unit
SYSC 2001
Control Unit

CPU
Sequencing
ALU Logic
Internal Control
Bus Unit
Control Unit
Registers Registers and
Decoders

Control
Memory
What about
Function?
2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 12
 Brief History of Computer Evolution
Two phases:
1. before VLSI 1945 – 1978
VLSI = Very Large
Scale Integration
• ENIAC
• IAS
• IBM see text discussion
• PDP-8
1. VLSI 1978  present day
• microprocessors !

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 13

 Cell 234 M
Growth in CPU Transistor Count

Pentium Evolution

PowerPC Evolution

Moore’s Law

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 14

 Speeding Up the Processor
 Pipelining
chicken / egg
 On board cache again !
 On board L1 & L2 cache
we’ll see
 Branch prediction
some of
 Data flow analysis these as the
course
 Speculative execution
progresses

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 15

 But Performance Mismatch!
 Processor speed increased
 Memory capacity increased
 Memory speed lags behind (and increasing slower than)
processor speed

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 16

 DRAM and Processor Characteristics

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 17

 Some Solutions
 Increase number of bits retrieved at one time
• Make DRAM “wider” rather than “deeper”
 Change DRAM interface
• Cache
 Reduce frequency of memory access
• More complex cache, and cache on chip
 Increase interconnection bandwidth
• High speed buses
• Hierarchy of buses

2007 Sept 06 SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt 18