Low Cost Embedded Core Test

Author: Ungureanu Estera Bianca

1. Introduction

A system on a chip or system on chip (SoC) is an integrated circuit

that integrates all components of a computer or other electronic system
into a single chip.

Testing of complex System on Chip circuits has to overcome the

following challenges:
To reach
better test quality than can be obtained by
pseudorandom test set application,
To reduce the tester memory requirements,
To reduce the amount of data transferred to/from the tested chip,
To keep the test time short and to keep the hardware overhead
acceptably low.

2. IEEE-1500 Standard

IEEE 1500 defines a standard for embedded-core test interfaces,

which includes a test wrapper, test ports, and wrapper control
signals.
A wrapper is an isolation boundary between a core and the rest of
the design.
IEEE-1500 hardware architecture :
Instruction Register (the Wrapper Instruction Register),
two data registers, the Wrapper Bypass Register (WBY) and
the Wrapper Boundary Register (WBR).
wrapper interface ports Wrapper Serial Ports (serial access)
and Wrapper Parallel Ports (parallel access)

3. Design for Testability (DfT) for

Low-Cost SoC Test

Reduced pin-count test RPCT for SoCs embedding IEEE-1500wrapped cores.

RPCT technique consits of performing Shift and Capture operations
with only a single flip-flop and no Update flip-flop.
Shift control (SC) is set to 1 for the Shift operation and 0 for the
Capture operation. Wrapper input cellWCI has to be set to 1 in the
Internal Test mode and Wrapper output cell WCO to 0 in the
External Test mode.
By embedding the scan-enable signal, and the scan input and
output ports, the number of pins needed to test a SoC is
significantly reduced to six.

 TAP

port pins:
TCK,
TMS,
TDI,
TDO,
TRST,
a clock pin.

4. Test Pattern Compaction

and Compression

In order to minimize the data transfer through the TAM, compacted

and compressed test sets are used, which is created in the
automatic test pattern generator (ATPG).

ATPG (Automatic Test Pattern Generation) is an technology used

to find an input sequence that, when applied to a digital circuit,
enables automatic test equipment to distinguish between the correct
circuit behavior and the faulty circuit behavior caused by defects.

Uncompressed test data generated by ATPG are stored as a plain

text file.
Simple loading of the file is not possible for large circuits.

Compression of the plain text data from the file has to be

performed which will be stored in memory.
After that the pattern overlapping compression is done.

The test pattern (TP) compression uses an algorithm for finding

contiguous and consecutive maximally overlapping scan chain
vectors for the actual scan chain vector. These vectors are checked
whether they match with one or more of TP, which were previously
generated.

The memory requirements low as for each test pattern only two
pointers are stored and after detecting a fault the corresponding
pattern is removed from the memory.

References

[1] Hyunbean Yi; Jaehoon Song; Sungju Park, "Low-Cost Scan Test
for IEEE-1500-Based SoC," Instrumentation and Measurement,
IEEE Transactions on , vol.57, no.5, pp.1071,1078, May 2008

[2] Novak, O.; Pliva, Z.; Jenicek, J.; Mader, Z.; Jarkovsky, M., "Self
Testing SoC with Reduced Memory Requirements and Minimized
Hardware Overhead," Defect and Fault Tolerance in VLSI Systems,
2006. DFT '06. 21st IEEE International Symposium on , vol., no.,
pp.300,308, 4-6 Oct. 2006

[3] Yervant Zorian, Avetik Yessayan, IEEE 1500 Utilization in SOC

Design and Test, International Test Conference, 2005 IEEE