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EI 502

Microprocessors
&
Microcontrollers
Part 5(16 bit 8086)

Debasis Das
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Intel 8086

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Features
Direct addressing of 1 MB memory space, 20

bit addressing bus


16 bit data bus, Bit/ byte/block operations
Multiplexed bus
Multiprocessor features
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Features
8086 is designed to operate in two modes,

Minimum and Maximum.


It can pre-fetch up to 6 instruction bytes from

memory and queue them in order to speed up


instruction execution.
Address ranges from 00000H to FFFFFH
Memory is byte addressable - Every byte has a

separate address

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8086 Microprocessor
Belongs to a popular microprocessor series
8086, 80186, 80286, 80386, 80486, Pentium

INTEL launched 8086 in 1978

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8086 Internal Architecture


8086 CPU has two parts which operate

independently (asynchronously) at the


same time

Bus Interface Unit


Execution Unit

8086 CPU

CPU functions
1.

Bus Interface
Unit (BIU)

Fetch

Decode
3. Execute

Execution Unit
(EU)

2.

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8088 Microprocessor
Processor that drove the first PC
It is a 8 bit processor
Handles 8 bit data, hence database is 8 bits.
Otherwise most details are same as the 8086

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BIU & EU Features


Both units operate asynchronously to give

the 8086 an overlapping instruction fetch


and execution mechanism which is called as
Pipelining. This results in efficient use of the
system bus and system performance.

BIU contains Instruction queue, Segment

registers, Instruction pointer, Address adder.

EU contains Control circuitry, Instruction

decoder, ALU, Pointer and Index register,


Flag register

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Bus Interface Unit


Sends out addresses for memory locations
Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input / Output ports

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Execution Unit
Tells BIU (addresses) where to fetch

instructions or data
Decodes & Executes instructions

Dividing the work between BIU & EU speeds up


processing

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8086 Block Diagram

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8086 Architecture

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Min/Max Pin-out
Modes

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Logical Signals

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8088 Details

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Min/Max Modes
Minimum and Maximum Modes
The minimum mode is selected by applying logic 1 to
the MN / MX# input pin. This is a single
microprocessor configuration.

The maximum mode is selected by applying logic 0

to the MN / MX# input pin. This is a multi micro


processors configuration.
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Signal Description-1

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Signal Description-2

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Signal Description
Max Mode

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Execution Unit
Main components are
Instruction Decoder
Control System
Arithmetic Logic Unit
General Purpose Registers
Flag Register
Pointer & Index registers
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Instruction Decoder
Translates instructions fetched from memory

into a series of actions which EU carries out

Control System
Generates timing and control signals to
perform the internal operations of the
microprocessor

Arithmetic Logic Unit


EU has a 16-bit ALU which can ADD,
SUBTRACT, AND, OR, increment, decrement,
complement or shift binary numbers
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Memory Organization

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General Purpose Registers


EU has 8 general

AH

purpose registers
BH
Can be individually
CH
used for storing 8-bit
data
DH
AL register is also called
Accumulator
AH
Two registers can be
BH
combined to form a 16bit register
CH
The valid register pairs
are AX, BX, CX, and
DH
DX
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AL
BL
CL
DL
AL

AX

BL

BX

CL

CX

DL

DX

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Flag Register
8086 has a 16-bit flag register
Contains 9 active flags
There are two types of flags in 8086
Conditional flags six flags, set or reset by EU

on the basis of results of some arithmetic


operations
Control flags three flags, used to control

certain operations of the processor


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Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
1.

CF

CARRY FLAG

2.

PF

PARITY FLAG

3.

AF

AUXILIARY CARRY

4.

ZF

ZERO FLAG

5.

SF

SIGN FLAG

6.

OF

OVERFLOW FLAG

7.

TF

TRAP FLAG

8.

IF

INTERRUPT FLAG

9. DF
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Conditional Flags
(Compatible with
8085, except OF)

Control Flags

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DIRECTION FLAG
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Bus Interface Unit


Main Components are
Instruction Queue
Segment Registers
Instruction Pointer

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Instruction Queue
8086 employs overlapped processing
When EU is busy decoding or executing current

instruction, the system bus of 8086 may not be in use.


At that time, BIU can use buses to fetch up to six

instruction bytes of the instructions next in program


BIU stores these pre-fetched bytes in a FIFO register

called Instruction Queue


When EU is ready for its next instruction, it simply

reads the instruction from the queue in BIU


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Instruction Pipeline
EU of 8086 does not have to wait for BIU to

fetch next instruction byte from memory


The presence of a queue in 8086 speeds up

the processing
Fetching the next instruction while the current

instruction executes is called Instruction look


ahead
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Instruction Pipeline

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Memory Segmentation
8086 has a 20-bit address bus
So it can address a maximum of 1MB of memory
8086 works with four 64KB segments at a time within this

1MB range (can be overlapped in exactly the same space)


These four memory segments are called
Code segment
Stack segment
Data segment
Extra segment
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Segment Registers
Holds the upper 16-bits of the starting

address for each of the segments


The four segment registers are
CS (Code Segment register)
DS (Data Segment register)
SS (Stack Segment register)
ES (Extra Segment register)
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Memory Address
Generation

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Code Segment
That part of memory from where BIU is currently

fetching instruction code bytes

Stack Segment
A section of memory set aside to store
addresses and data while a subprogram
executes, accommodates stacks

Data & Extra Segments


Used for storing data values to be used in the
program
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Reserved Memory
Locations

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Min Mode Logical


Pin out

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Min Mode
Interface-1
When the Minimum mode operation is selected, the 8086

provides all control signals needed to implement the


memory and I/O interface
The minimum mode signal can be divided into the
following basic groups: address/data bus, status, control,
interrupt and DMA.
Address/Data Bus : these lines serve two functions.
As an address bus is 20 bits long and consists of signal
lines A0 through A19. A19 represents the MSB and A0
LSB. A 20bit address gives the 8086 a 1Mbyte memory
address space.
Independent I/O address space which 64K bytes in length
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Min Mode
Interface-2
The 16 data bus lines D0 through D15 are

actually multiplexed with address lines A0


through A15 respectively. The bus works as an
address bus during first machine cycle and as a
data bus during next machine cycles. D15 is the
MSB and D0 LSB
When acting as a data bus, they carry read/write

data for memory, input/output data for I/O


devices, and interrupt type codes from an
interrupt controller
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Min Mode
Interface-3
Status signal : The four most significant address lines

A19 through A16 are also multiplexed but in this case


with status signals S6 through S3. These status bits are
output on the bus at the same time that data are
transferred over the other bus lines.
Bit S4 and S3 together form a 2 bit binary code that
identifies which of the 8086 internal segment registers
are used to generate the physical address output on
the address bus during the current bus cycle
Code S4,S3 = 00 identifies a register known as extra
segment register as the source of the segment address

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Min Mode
Interface-4

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Min Mode
Interface-5
Status line S5 reflects the status of another internal

characteristic of the 8086. It is the logic level of the


internal enable flag. The last status bit S6 is always
at the logic 0 level
Control Signals : The control signals are provided to

support the 8086 memory & I/O interfaces. They


control functions such as when the bus is to carry a
valid address, in which direction data are to be
transferred over the bus, when valid write data are
on the bus and when to put read data on the system
bus
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Min Mode
Interface-6
ALE is a pulse to logic 1 that signals external circuitry

when a valid address word is on the bus. This address


must be latched in external circuitry on the 1-to-0
edge of the pulse at ALE.
Another control signal that is produced during the bus
cycle is BHE bank high enable. Logic 0 on this used as
a memory enable signal for the most significant byte
half of the data bus D8 through D1. These line also
serves a second function, which is as the S7 status line
Using the M/IO and DT/R lines, the 8086 signals which
type of bus cycle is in progress and in which direction
data are to be transferred over the bus.
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Min Mode
Interface-7
The logic level of M/IO tells external circuitry whether a

memory or I/O transfer is taking place over the bus. Logic


1 at this output signals a memory operation and logic 0
an I/O operation.
The direction of data transfer over the bus is signalled by
the logic level output at DT/R. When this line is logic 1
during the data transfer part of a bus cycle, the bus is in
the transmit mode. Therefore, data are either written into
memory or output to an I/O device
On the other hand, logic 0 at DT/R signals that the bus is
in the receive mode. This corresponds to reading data
from memory or input of data from an input port
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Min Mode
Interface-8
The signal read RD and write WR indicates that a read

bus cycle or a write bus cycle is in progress. The 8086


switches WR to logic 0 to signal external device that
valid write or output data are on the bus
On the other hand, RD indicates that the 8086 is
performing a read of data of the bus. During read
operations, one other control signal is also supplied.
This is DEN ( data enable) and it signals external
devices when they should put data on the bus
There is one other control signal that is involved with
the memory and I/O interface. This is the READY
signal
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Min Mode
Interface-9
READY signal is used to insert wait states into the

bus cycle such that it is extended by a number of


clock periods. This signal is provided by an external
clock generator device and can be supplied by the
memory or I/O subsystem to signal the 8086 when
they are ready to permit the data transfer to be
completed.
Interrupt signals : The key interrupt interface signals
are interrupt request (INTR) and interrupt
acknowledge( INTA)
INTR is an input to the 8086 that can be used by an
external device to signal that it need to be serviced
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Min Mode
Interface-10
Logic 1 at INTR represents an active interrupt request.

When an interrupt request has been recognized by


the 8086, it indicates this fact to external circuit with
pulse to logic 0 at the INTA output
The TEST input is also related to the external interrupt
interface. Execution of a WAIT instruction causes the
8086 to check the logic level at the TEST input
If the logic 1 is found, the MPU suspends operation
and goes into the idle state. The 8086 no longer
executes instructions, instead it repeatedly checks the
logic level of the TEST input waiting for its transition
back to logic 0
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Min Mode
Interface-11
As TEST switches to 0, execution resume with the next

instruction in the program. This feature can be used to


synchronize the operation of the 8086 to an event in
external hardware.
There are two more inputs in the interrupt interface:
the non-maskable interrupt NMI and the reset interrupt
RESET
On the 0-to-1 transition of NMI control is passed to a
non-maskable interrupt service routine. The RESET
input is used to provide a hardware reset for the 8086.
Switching RESET to logic 0 initializes the internal
register of the 8086 and initiates a reset service routine
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Min Mode
Interface-12
DMA Interface signals :The direct memory access

DMA interface of the 8086 minimum mode consist of


the HOLD and HLDA signals
When an external device wants to take control of the
system bus, it signals to the 8086 by switching
HOLD to the logic 1 level. At the completion of the
current bus cycle, the 8086 enters the hold state. In
the hold state, signal lines AD0 through AD15,
A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR,
DEN and INTR are all in the high Z state. The 8086
signals external device that it is in this state by
switching its HLDA output to logic 1 level
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Max Mode
Block Diagram

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Max Mode
Interface-1
When the 8086 is set for the maximum-mode

configuration, it provides signals for implementing a


multiprocessor / coprocessor system environment
By multiprocessor environment we mean that one
microprocessor exists in the system and that each
processor is executing its own program
Usually in this type of system environment, there are
some system resources that are common to all
processors
They are called as global resources. There are also
other resources that are assigned to specific processors.
These are known as local or private resources
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Max Mode
Interface-2
In multiple processor situation a second

processor is in the system. Both processors do


not access the bus at the same time
One passes the control of the system bus to
the other and then may suspend its operation
In the maximum-mode 8086 system, facilities
are provided for implementing allocation of
global resources and passing bus control to
other microprocessor or coprocessor.

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Max Mode
Interface-2
8288 Bus Controller Bus Command and Control

Signals: 8086 does not directly provide all the signals


that are required to control the memory, I/O and
interrupt interfaces
Specially the WR, M/IO, DT/R, DEN, ALE and INTA,
signals are no longer produced by the 8086. Instead it
outputs three status signals S0, S1, S2 prior to the
initiation of each bus cycle. This 3- bit bus status code
identifies which type of bus cycle is to follow
S2,S1,S0 are input to the external bus controller
device, the bus controller generates the appropriately
timed command and control signals
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Max Configuration
Using 8288 Bus Controller

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8288 Pin out

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Max Mode
Interface-3

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Max Mode
Interface-4
The 8288 produces one or two of these eight

command signals for each bus cycles. For instance,


when the 8086 outputs the code S2S1S0 equals 001,
it indicates that an I/O read cycle is to be performed
If the code 111 is output by the 8086, it is signalling
that no bus activity is to take place
The control outputs produced by the 8288 are DEN,
DT/R and ALE. These 3 signals provide the same
functions as those described for the minimum system
mode. This set of bus commands and control signals
is compatible with the Multibus (an industry standard)
for interfacing microprocessor systems.
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Max Mode
Interface-5
8289 Bus Arbiter Bus Arbitration and Lock Signals

: This device permits processors to reside on the


system bus. It does this by implementing the
Multibus arbitration protocol in an 8086-based
system
Addition of the 8288 bus controller and 8289 bus
arbiter frees a number of the 8086 pins for use to
produce control signals that are needed to support
multiple processors
Bus priority lock ( LOCK) is one of these signals. It is
input to the bus arbiter together with status signals
S0 through S2.
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8289 Block Diagram

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8289 Pin Out

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Max Mode
Interface-6
The output of 8289 are bus arbitration signals:

bus busy (BUSY), common bus request (CBRQ),


bus priority out (BPRO), bus priority in (BPRN),
bus request (BREQ) and bus clock (BCLK).
They correspond to the bus exchange signals of
the Multibus and are used to lock other processor
off the system bus during the execution of an
instruction by the 8086
In this way the processor can be assured of
uninterrupted access to common system
resources such as global memory.
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Max Mode
Interface-7
Queue Status Signals : Two new signals that are

produced by the 8086 in the maximum-mode system


are queue status outputs QS0 and QS1. Together
they form a 2-bit queue status code, QS1QS0
Following table shows the four different queue status

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Max Mode
Interface-8
Local Bus Control Signal Request / Grant Signals:

In a maximum mode configuration, the minimum


mode HOLD, HLDA interface is also changed. These
two are replaced by request/grant lines RQ/ GT0 and
RQ/ GT1, respectively. They provide a prioritized bus
access mechanism for accessing the local bus.

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Instruction Pointer (IP) Register


A 16-bit register
Holds 16-bit offset, of the next instruction byte

in the code segment


BIU uses IP and CS registers to generate the 20-

bit address of the instruction to be fetched from


memory
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Stack Segment (SS) Register


Stack Pointer (SP) Register
Upper 16-bits of the starting address of stack

segment is stored in SS register


It is located in BIU
SP register holds a 16-bit offset from the start of

stack segment to the top of the stack


It is located in EU
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Other Pointer & Index Registers


Base Pointer (BP) register
Source Index (SI) register
Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data word

in one of the segments


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Memory Space

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8086 System Related


Chips

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8286/7 Octal
Transceivers

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8 Bit I/O Ports


8282/8283

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8284A Clock generator

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Instruction Set

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Instruction Format

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Addressing Modes
Addressing mode indicates a way of locating data or

operands
Depending upon the data types used in the
instruction and the memory addressing modes, any
instruction may belong to one or more addressing
modes, or some instruction may not belong to any of
the addressing modes
Addressing modes describe the types of operands and
the way they are accessed for executing an
instruction. Instructions may be categorized as
Sequential control flow instructions and
Control transfer instructions
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Instruction Type
Modes
Sequential control flow instructions are the

instructions, which after execution, transfer control


to the next instruction appearing immediately after
it (in sequence) in the program
For example, the arithmetic, logical, data transfer and

processor control instructions are sequential control


flow instructions

The control transfer instructions, on the other hand,

transfer control to some predefined address


somehow specified in the instruction after their
execution. For example, INT, CALL, RET and JUMP
instructions fall under this category
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Sequential Control
Flow
Modes

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Immediate Mode
In this type of addressing, immediate data is a

part of instruction, and appears in the form of


successive byte or bytes.
Example: MOV AX, 0005H

In the above example, 0005H is the immediate


data. The immediate data may be 8-bit or 16bit in size

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Direct Mode
In the direct addressing mode, a 16-bit memory

address (offset) is directly specified in the


instruction as a part of it.
Example: MOV AX, [5000H]

Here, data resides in a memory location in the


data segment, whose effective address may be
computed using 5000H as the offset address
and content of DS as segment address. The
effective address, here, is 10H*DS+5000H
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Register Mode
In register addressing mode, the data is

stored in a register and it is referred using the


particular register. All the registers, except IP,
may be used in this mode.

Example: MOV BX, AX

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Register Indirect
Sometimes, the address of the memory location, which

contains data or operand, is determined in an indirect way,


using the offset registers. This mode of addressing is known
as register indirect mode. In this addressing mode, the offset
address of data is in either BX or SI or DI registers. The
default segment is either DS or ES. The data is supposed to
be available at the address pointed to by the content of any
of the above registers in the default data segment.
Example: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset


address is in BX. The effective address of the data is given as
10H*DS+ [BX]
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Indexed
In this addressing mode, offset of the operand

is stored in one of the index registers. DS and


ES are the default segments for index
registers SI and DI respectively. This mode is a
special case of the above discussed register
indirect addressing mode.
Example: MOV AX, [SI]

Here, data is available at an offset address


stored in SI and DS. The effective address, in
this case, is computed as 10H*DS+ [SI]
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Register Relative
In this addressing mode, the data is available

at an effective address formed by adding an


8-bit or 16-bit displacement with the content
of any one of the registers BX, BP, SI and DI in
the default (either DS or ES) segment. The
example given before explains this mode.
Example: MOV Ax, 50H [BX]

Here, effective address is given as


10H*DS+50H+ [BX]
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Based Indexed
The effective address of data is formed, in this

addressing mode, by adding content of a base


register (any one of BX or BP) to the content
of an index register (any one of SI or DI). The
default segment register may be ES or DS.
Example: MOV AX, [BX] [SI]

Here, BX is the base register and SI is the index


register. The effective address is computed as
10H*DS+ [BX] + [SI]
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Relative Based
Indexed
The effective address is formed by adding an

8-bit or 16-bit displacement with the sum of


contents of any one of the bases registers (BX
or BP) and any one of the index registers, in a
default segment.
Example: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is


a base register and SI is an index register. The
effective address of data is computed as
160H*DS+ [BX] + [SI] + 50H
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Control Transfer
Modes

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Basis of Modes
For the control transfer instructions, the addressing modes

depend upon whether the destination location is within


the same segment or a different one. It also depends upon
the method of passing the destination address to the
processor. Basically, there are two addressing modes for
the control transfer instructions, viz. inter-segment and
intra-segment addressing modes.
If the location to which the control is to be transferred lies

in a different segment other than the current one, the


mode is called inter-segment mode. If the destination
location lies in the same segment, the mode is called
intra-segment.
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Control Transfer
Modes
Modes
Inter segment

Inter segment direct

Inter segment indirect

Intra segment

Intra segment direct

Intra segment indirect

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Instruction Categories
Categories
Data Transfer
Arithmetic
String
Logical
Shift
Rotate
Program Execution

Categories

Interrupt
HLL Support
Processor Control
Bit Manipulation
Iteration Control

Transfer
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Data Transfer-1
MOV destination, source
PUSH source
PUSH / PUSHAD
POP destination
POPA / POPAD
XCHG destination, source
XLAT

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Data Transfer-2
MOXZX destination, source
MOVSZ destination, source
CBW
CDW
CWDE
CDQ
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

88

Data Transfer-3
LEA register, source
LDS register, source
LSS register, source
LES register, source
LGS register, source
LFS register, source

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

89

Data Transfer-4
LAHF
SAHF
PUSHF
POPF
PUSHFD
POPFD
STC
CLC
CMC
STD
CLD
CLTS
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

90

Data Transfer-5
IN accumulator, port number
OUT port number, accumulator

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

91

Arithmetic-1
ADD destination, source
ADC destination, source
INC destination
AAA
DAA
SUB destination, source
SBB destination, source
DEC destination

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

92

Arithmetic-2
NEG register
CMP destination, source
AAS
DAS
MUL source
AAM
DIV source
IDIV source
AAD
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

93

Logical-1
NOT destination
AND destination, source
OR destination, source
XOR destination, source
TEST destination, source
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

94

Logical-2
SAL / SHL Destination, Count
SAL BX, 01
SAL BP, CL
MOV CL, 04H
SAL AL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

95

Logical-3
SHR Destination, Count
SHR BP, 01
SHR AL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

96

Logical-4
SAR Destination, Count
SAR DI, 1
SAR AL, 01

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

97

Logical-5
ROL Destination, Count
ROL AX, 1
ROL BL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

98

Logical-6
RCL Destination, Count
RCL AX, 1
RCL BL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

99

Logical-7
ROR Destination, Count
ROR BL, 01
ROR AL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

100

Logical-8
RCR Destination, Count
RCR BL, 01
RCR AL, CL

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

101

Program Execution Transfer


Call Procedure
CALL SQRT
CALL BX
CALL WORD PTR(BX)

RET

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

102

Jump Instructions-1
JMP label

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

103

Jump Instructions-2

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

104

Jump Instructions-3

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

105

Iteration Control Instructions

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

106

Interrupt
STI
CLI
INT type
INTO
IRET

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

107

Bit Manipulation
BT

Bit test and put specified bit in carry flag.


E.g. BT ECX, 4
BTS
BTR
BTC
BSF
BSF BX, CX
BSR
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

108

String Instructions
MOVS / MOVSB / MOVSW / MOVSD
INS / INSB / INSW
OUTS / OUTSB / OUTSW
CMPS / CMPSB / CMPSW / CMPSD
SCAS / SCASB / SCABW / SCASD
LODS / LODSB / LODSW / LODSD
STOS / STOSB / STOSW / STOSD
REP / REPE / REPZ / REPNE / REPNZ

Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

109

Processor Control
HLT
WAIT
ESC
LOCK
NOP
Sep-Oct 2011

Mallabhum Institute of Technology

Debasis Das

110