Basics of

Timing Analysis

Prerequisites

Knowledge of Digital Design

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Objective

Importance of Timing Analysis

Timing Fundamentals
How to perform Timing Checks

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Scope

Need for Timing Analysis

Timing Fundamentals
Timing Analysis
Introduction
Basic
Advanced
Timing Optimization

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Day 1

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Why Timing Analysis Needed?

Requirement specification of any digital system consists of Functional Spec

and Timing Spec.
Chip

Functional
Specifications

RTL

GDS-II

Timing
Specifications

Functional
Verification

GLS

LEC

STA

Functional verification and LEC takes care of verifying the implementation

of the functional Spec.
GLS and STA takes care of verifying the implementation of Timing
Specifications.

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Static Verification Flow

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What is Timing Analysis

Any digital circuit comprises of sequential elements such as DFF,

Memories, PLL etc.

Each element has its own operating timing limits

To validate that each component meets its own operating restriction.

Each component has its own limit which are bound by the variations in
the operating environment.

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Corner Analysis

The behavior of all components depend on three parameters:

Process variation (P)
Supply voltage (V)
Operating Temperature (T)

Because of these parameters governing the behavior of the components,

we have three corners
Fast corner (Min)
Slow corner (Max)
Typical corner

Performance of a circuit depends on the delays of the path

To guarantee timing spec be met under any parameter settings, delay is
measured at the corners of the parameter space.
Measurements are provided in the cell libraries.
Corners are expected to bound the performance.

07/25/15 - page 9

Design Corners

Best Case/Fast Corner/ Min Corner :

Fast process, Highest voltage and Lowest temperature
Checks for the Hold time

Worst Case/Slow Corner/Max Corner:

Slow process, Lowest voltage and Highest temperature
Checks for Setup Time

Typical Corner :
Checks for both Hold and Setup Time.
Provides an approximate estimate of the frequency that can be met

07/25/15 - page 10

Timing Analysis at PVT corners

Timing analysis should be performed at PVT corners to determine the

timing margins
Take the timing parameters at each extreme PVT corner to calculate the
timing margins
All active devices in the circuit will specify Min, Typ, and Max values
for delays.
We use Min and Max values to find out the worst case minimum delays
and worst case maximum delays
Consider separate worst case conditions for data and clock

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Timing Fundamentals

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Concept of D Latch

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Timing diagram of D latch with Enable ( C )

When C is high, Q just follows the input.

(It is called a transparent latch)

When C is low, it just retains its state.

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Useful timing parameters for a D latch

Four different delay parameters are shown.
Signals propagate from C or D input to Q output.
At transitions 1 and 4, latch is initially closed so D input is opposite of
Q output.
When C goes to 1, latch opens up and Q output changes after delay
tpLH(CQ) or tpHL(CQ) .
At transitions 2 and 3, the C input is already 1 and the latch is open so
Q transparently follows the transition on D with delay t pLH(DQ) or
tpHL(DQ).

07/25/15 - page 15

Useful timing parameters for a D latch (Contd)

D Input must not change in the (shaded) window of time around the
falling edge of C.

Window begins at time tsetup before the falling (latching) edge of C

which is the setup time.

Window ends at time thold afterward which is the hold time.

If D changes at any time during the setup- and hold- time window, the
output of the latch is unpredictable and may become metastable.

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Metastability

Metastability is the state that exist between either valid digital logic
state.
Digital circuits have two stable states - but all have a third metastable
state halfway between 0 and 1.
When the setup and hold times of a latch/flip-flop are not met, it could
be put into the metastable state.
Noise will be amplified and push the latch/flip-flop one way or other.

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Edge triggered D Flip-Flop

Positive edge triggered D F/F combines a pair of D latches and CLK

signal.
Samples D input and changes its Q and QN outputs only at the rising
edge of a CLK signal.

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Timing Behavior of Positive-edge triggered D Flip-Flop

It has a setup- and hold-time window during which the D input must not
change.
This window occurs around the triggering edge of CLK.
If setup and hold times are not met, the flip-flop output goes to
metastable state.

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Timing Analysis

Types of Timing Analysis :

Dynamic Timing Analysis

Static Timing Analysis

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Dynamic Timing Analysis

Dynamic Timing Analysis

Determines the full behavior of the circuit for a given set of input
stimulus vectors.
Reuse of Functional Verification.
Needs to be exhaustive to cover each and every path.
Limitation of Dynamic Timing Analysis
Basic problem is controllability for complex circuits.
Consumes more run time
Dependent on stimulus vectors

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An example circuit

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Static Timing Analysis

Static Timing Analysis

Method to determine if a design meets timing constraints w/o having to
simulate the design with vectors.

STA consists of three major steps:

Break the design into Fan-in Cone for each destination flop .

Delay of each Fan-in cone is calculated using formal, mathematical

techniques instead of vectors.

All path delays are checked against timing constraints

Does not use dynamic logic simulation.

100 % exhaustive for sequential input to sequential output.

07/25/15 - page 23

Static Timing Analysis (Contd)

An STA tool
Takes in a circuit and its timing constraints
Computes its performance bounds
Compares them against its timing constraints
Outputs a pass or fail

Cone Based Analysis

[Source : http://www.tauworkshop.com/04_Slides/Tseng-False.pdf]
07/25/15 - page 24

STA Advantages and Disadvantages

Advantages:
Speed (Faster than dynamic simulation)
Capacity of handling full chip
Exhaustive Timing coverage
Vectors not required
Process variation across die can be modeled
Assertions and reports are concise and easy to interpret

Disadvantages:
Pessimistic (too conservative).
If you are doing worst case analysis then path delay considered is worst
for all the elements within the path where-as in actual scenario it might
not be so worse.
It might happen that the PVT may not correspond to the real working
environment but still we need to close timing in all corners.
Difficult to get correct timing models/parameters for Analog components to
perform STA. Not a limitation from STA tool point of view.

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Inputs & Outputs of STA

Inputs

Netlist (verilog/VHDL) : The gate level circuit description.

Constraints (sdc/tcl) : The design related data
Net Delays
Parasitics (SPEF) : These are the parasitics of the design extracted
from physical design tools.
OR
Netlist (verilog/VHDL) : The gate level circuit description.
SDF : Standard Delay Format file containing back-annotated delays.
Models (lib/db): The delay model of every cell in the library

Outputs
Reports : The timing paths report which can be used for analyzing.

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Timing Analysis

Timing Analysis is split into three sections :

Introduction
Basic
Advance

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Timing Analysis

Introduction

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Delays

Gate delay
Transistors within a gate, take a finite amount of time to switch. This
means that a change on the input of a gate takes a finite amount of time
to cause a change on the output.
Net delay
The delay between the time a signal is first applied to the net and the
time it reaches other devices connected to that net.
A

Stage Delay
A

VDD

Y
A

Gate
delay

Net delay
(Interconnect)

Y
VSS

Transistor
Representation

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 29

Gate Delay
Delay through a cell is often determined by the cells intrinsic delay, load
that it is driving, and input transition (slew)
Transition is the time it takes for the pin to change state

A
Propagation Delay (inverting)

Propagation Delay (non-inverting)

Voltage
Vmax

Voltage
Input Signal

Vmin

Output Signal
50%

Vmax

90%
10%

Cell Delay

Slew
Time

Vmin

Input Signal
50%

Output Signal
90%
10%

Cell Delay
Slew
Time

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 30

Net Delay

Interconnect causes the timing arc to be from pin to pin

These net delays are computed using wireload model estimation, or are
computed using back-annotated delay information if available
^ -> ^
A

A
v -> v

^ -> ^
v -> v

50%
50%

Net Delay

Net Delay

50%
50%

[Source : Timing Analysis Basics presentation from Cadence]

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Timing Paths
What is timing point ?
Node at which timing data is present
What is a Timing path?
A timing path is a point-to-point path in a design which can
propagate data from from one flip-flop to another
Each path has a startpoint and an endpoint
Startpoints (Input ports, Clock pins of flip-flops)
Endpoints ( Output ports, Data input pins of flip-flops)
Timing Point
INPUT

CLOCK

07/25/15 - page 32

D
Q
FF1

D
Q
FF2

OUTPUT

Setup & Hold Times

DATA
CLK

CLK

PRE
D

Tsu Th

Q
CLR

DATA

Valid

Setup Time: the amount of time the synchronous input (D) must be stable
before the active edge of clock
Hold Time: the amount of time the synchronous input (D) must be stable
after the active edge of clock.
Together, the setup time and hold time form a Data Required Window, the
time around a clock edge in which data must be stable.

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 33

Setup Time

Setup Margin
The data valid time available after meeting the setup requirement

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Hold Time

Hold Margin
The data valid time available after meeting the hold requirement

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Setup and Hold Time (Contd)

Setup Time Requirement

tclk,min > tffpd,max + tcomb,max + tsetup

Setup time margin

= tclk,min - tffpd,max - tcomb,max - tsetup

> 0 for guaranteed operation

Hold Time Requirement
tffpd, min + tcomb,min > thold,min

Hold time margin

= tffpd, min + tcomb,min - thold,

0 for guaranteed operation

Assumption in the above formulae
Interconnect delays & Clock Skews ignored.
Effect of Interconnect delay & clock skew can be analyzed in a similar
fashion as an exercise.

07/25/15 - page 36

Lab Session 1

For a sequential circuit, the following timing parameters are given tcomb = 1 ns, min and 8 ns, max
tffpd = 2 ns, min and 10 ns, max
tsetup = 2 ns, min & max
thold = 1 ns, min & max
Calculate Setup Margin at 25 Mhz clk frequency, Maximum frequency and
the hold margin?

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Day 2

07/25/15 - page 38

Timing Analysis

Basics

07/25/15 - page 39

Arrival Time, Required Time & Slack

Arrival time:
Time elapsed for a signal to arrive at a certain point.
To calculate the arrival time, delay calculation of all the component of the
path will be required.
Required time:
Latest time at which a signal can arrive without making the clock cycle longer
than desired.
Slack:
It is the difference between the required time and the arrival time.
This is the amount of time by which a violation is avoided
E.g.: for a setup constraint, if a signal must reach a cell input at no later than
8 ns and is determined to arrive at 5 ns, the slack is 3 ns.
A slack of 0 means that the constraint is just barely satisfied.
A negative slack indicates a timing violation.
07/25/15 - page 40

Setup & Hold Violations

Two types of violation :

Hold violation
Setup Violation
Hold violation is caused when the clock travels slower than the path from
one register to another allowing data to penetrate two registers in the
same clock tick, or might destroy the integrity of the latched data.
Setup Violation is caused if the data signal gets delayed from the source
flip-flop, so that the data signal has that much less time to reach the
destination flip-flop before the next clock tick.
Which is more dangerous setup violation or hold violation?

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Data Arrival Time

The time for data to arrive at destination registers D input

Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
REG1

Comb.
Logic

PRE

Tclk1

Tdata

CLR

REG2
PRE

Q
CLR

TCO
Launch
Edge

Tclk1
REG1.CLK

Tco

REG1.Q

Data Valid

Tdata
REG2.D

Data Valid

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 42

Clock Arrival Time

The time for clock to arrive at destination registers clock input

Clock Arrival Time = latch edge + Tclk2

REG1
PRE

REG2

Comb.
Logic

PRE

CLR

Q
CLR

Tclk2

Latch
Edge
CLK

REG2.CLK
[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 43

Tclk2

Data Required Time - Setup

The minimum time required for the data to get latched into the destination
register
Data Required Time = Clock Arrival Time Tsu
REG1
PRE

REG2

Comb.
Logic

PRE

CLR

Q
CLR

Tclk2
Latch
Edge
CLK

Tclk2
Data must be
valid here

Tsu

REG2.CLK
REG2.D

Data Valid

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 44

Data Required Time - Hold

The minimum time required for the data to get latched into the
destination register
Data Required Time = Clock Arrival Time + Th
REG1
PRE

REG2

Comb.
Logic

PRE

CLR

CLR

Tclk2

CLK
Data must
remain valid
to here

Tclk2

Th

REG2.CLK
REG2.D

Data Valid

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 45

Th
Latch
Edge

Setup Slack

The margin by which the setup timing requirement is met. It ensures

launched data arrives in time to meet the latching requirement.
REG1
D

Tdata

Comb.
Logic

PRE

Tclk1

PRE

CLR

CLK
REG1.CLK

Tclk2

Tclk1
Tco
Data Valid

Tdata
REG2.D

Data Valid

Tclk2

Tsu

Setup
Slack

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 46

Tsu
Latch
Edge

REG1.Q

REG2.CLK

Q
CLR

TCO

Launch
Edge

REG2

Setup Slack (contd)

Setup Slack = Data Required Time Data Arrival Time

Positive slack
Timing requirement met
Negative slack
Timing requirement not met

CALCULATION:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time FF2
Slack = Required time - Arrival time (since we want data to arrive before it is required)
clock adjust = clock period (since setup is analyzed at next edge)

07/25/15 - page 47

Hold Slack

The margin by which the hold timing requirement is met. It ensures

latch data is not corrupted by data from another launch edge. It also
prevents double-clocking.
REG1
PRE

Tclk1

Comb.
Logic

Tdata

REG2
PRE

CLR

Q
CLR

TCO

Tclk2

Th

Next Launch
Edge
CLK

Latch
Edge

Tclk1

REG1.CLK
REG1.Q

Tco
Data Valid

Tdata
REG2.D

Data Valid

Tclk2
REG2.CLK

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 48

Th

Hold
Slack

Hold Slack (Contd)

Hold Slack = Data Arrival Time Data Required Time

Positive slack
Timing requirement met
Negative slack
Timing requirement not met

CALCULATION:
Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)
Required time = clock adjust + clock delay FF2 (max) + hold time FF2
Slack = Arrival time - Required time (since we want data to arrive after it is required)
clock adjust = 0 (since hold is analyzed at same edge)

07/25/15 - page 49

Recovery & Removal

Recovery time is the minimum time that an asynchronous control must

be stable before the clock active-edge transition, when async signal is
asserted.

Removal time is the minimum length of time that an asynchronous

control must be stable after the clock active-edge transition, when async
signal is deasserted.
SET
D

CLK
ASYNC
clock
recovery time
async_in

07/25/15 - page 50

removal time

Q
CLR

I/O Analysis

Analyzing I/O performance in a synchronous design uses the same slack

equations
Must include external device & PCB timing parameters
Data
Arrival
Path
ASSP or FPGA/CPLD
reg1

reg2

Tdata

PRE

FPGA/CPLD or ASSP
PRE

C
CLR

CLR

TCO

Tsu/Th
Tclk2

Data
Arrival
Path

*
L

OSC

Data
Required
Path

[Source : Alteras Timing Analysis Introduction presentation]

07/25/15 - page 51

How many timing paths?

Path 1

Path 2

Path 3

Path 4

Path 1 starts at an input port and ends at the data input of a sequential element.
Path 2 starts at the clock pin of a sequential element and ends at the data input
of a sequential element.
Path 3 starts at the clock pin of a sequential element and ends at an output port.
Path 4 starts at an input port and ends at an output port.

07/25/15 - page 52

How many timing paths? (Contd)

Register to Register
Input port to Register
Set the data arrival time at the port
Register to Output port
Set the port external delay
Input port to Output port
Input to Reg

Reg to Reg

IN_1

OUT_1

FF1

IdlClk

FF2
IN_2

Reg to Output

Input to Output

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 53

OUT_2

Understanding Timing Paths: Reg to Reg

Gate + Wire delay

D Q
Clock to Q

D Q
Setup
Time

_
C Q

_
C Q

Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 54

Understanding Timing Paths: Input to Reg

Input Delay = clk --> q t comb1

Outside World

Block Being Constrained

Gate + Wire delay

Input Delay
Clock to Q

D Q
_
C Q

Clock
Root

Comb1

Gate +
Wire delay

D Q

Comb2
Setup
Time

_
C Q

Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 55

Understanding Timing Paths: Reg to Output

External_delay = comb delay + setup

External_delay = comb delay - hold time
Block Being Constrained

Outside World
External Delay

Clock to Q

D Q
_
C Q

D Q

Comb1
Gate +
Wire delay

Setup
Gate + Time

_
C Q

Wire delay

0 Clock
Root

Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 56

Understanding Timing Paths: Input Port to Output Port

Input delay and output delay are set with respect to a clock
Default single-cycle
Setup requirement:
Comb delay < clock period - input delay - external delay
Hold requirement:
Comb delay > clock period - input delay - external delay
Combinational paths have no clocks defined for the module
Setup requirement:
Comb delay =< (delay set with set_path_delay_constraint -late) input_delay -external_delay
Hold requirement:
Comb delay >= (the delay set with set_path_delay_constraint -early)
- input_delay - external_delay

[Source : Timing Analysis Basics presentation from Cadence]

07/25/15 - page 57

Primetime Timing Report

Four Sections in a Timing Report

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The Header

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Data Arrival Section

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Data Required Section

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Lab Session 2
R: Cell delay when Output pin transitions from 0->1
F: Cell delay when Output pin transitions from 1->0

(i)
(ii)

What is the longest data arrival time?

What is the shortest data arrival time?

07/25/15 - page 62

Lab Session 3
Delays given are :
U1 = 1.1 ns, U2 = 1.1 ns, U3 = 1 ns, U4 = 0.11ns, U5 = 0.11ns
Clk2Q = 0.5 ns max, 0.4 ns min, Tsu = 0.21ns
TH= 0.1ns
Calculate (i) Data Arrival Time for setup, (ii) Data Required time for setup,
(iii) Setup Slack, i.e. is setup timing met? (iv) Data Required time for
Hold, (v) Hold Slack, i.e. is hold timing met?

07/25/15 - page 63

Lab Session 4
Perform Setup/Hold Analysis for the following circuitry and report slack. If
there are any timing violations, suggest fixes that can be done on the
circuit so that the circuit operates within the stated timing objective.
Frequency of CLK = 100 MHz
Setup time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 2 ns
Hold time of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 1 ns
Clock to Q delay of Flip-Flop (FF1, FF2, FF3, FF4 etc) = 300 ps.
Propagation delay of Buffers in the library (B1, B2, B3, B4, B5 etc) is 500
ps.
Propagation delay of 2:1 Mux in the library (M1 etc) from input IN1/IN2
to OUT is 1 ns.
Propagation delay of 2:1 Mux in the library (M1 etc) from input SEL to
OUT is 500 ps.
Assume all net delays as zero.
07/25/15 - page 64

Lab Session 4 (Contd)

07/25/15 - page 65

Lab Session 5
For the circuit shown below, find the maximum frequency of CLK? Also
draw the output waveform of SIGA for input CLK at the maximum
frequency.
Setup time of D Flip-Flop (D-FF) = 2 ns
Hold time of D Flip-Flop (D-FF) = 1 ns
Clock to Q delay of Flip-Flop (D-FF) = 500 ps.
Propagation delay of the Invertor (I1) = 500 ps.
Assume all net delays as zero.

07/25/15 - page 66

Lab Session 6
In the circuit given below what is the maximum delay allowed in the combo
cloud to operate the circuit at 100MHz.
Clk to Q of Flop = 1ns
Flop Setup Time = 700ps
Flop Hold Time = 300ps
(Assume Wire Delays and Inverter Delay I1 are Zero and the Duty cycle is
50%)

07/25/15 - page 67

Lab Session 7

What is the function of this circuit?

Which of the following is correct? (Answer the questions based on the figure below)

Compared to Figure 1 In Figure 2 FF2 Setup margin increased and Hold margin increased
b) Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and hold margin increased
c)
Compared to Figure 1 In Figure 2 FF2 Setup margin decreased and hold margin decreased
d) Compared to Figure 1 In Figure 2 FF2 Setup margin increased and hold margin decreased
Ans: (b)
a)

07/25/15 - page 68

Summary

Till now we have covered the following topics :

Need for Timing Analysis

Timing Fundamentals
Timing Analysis
Introduction
Basic

07/25/15 - page 69

Bibliography

https://solvnet.synopsys.com/
http://vsbu.wipro.com/Rep/Trainings/ASIC/vsbu24/VSBU24_Static_Timi
ng.ppt
http://vsbu.wipro.com/Rep/Trainings/ASIC/implementerTrg/articles/oth
ers/STA001_timing_basics.ppt

07/25/15 - page 70