CS1104 Lecture 14: Introduction to Algorithmic State Machines (ASM

CS1104 Computer Organization
http://www.comp.nus.edu.sg/~cs1104
Aaron Tan Tuck Choy

School of Computing
National University of Singapore
CS1103
Lecture 14: Introduction to

Algorithmic State Machines (ASM)
Large Digital Systems

Top-Down Approach
Controller and Data Processor
Flowcharts
ASM Charts
Components of ASM Charts
ASM Charts: An Example
Register Operations
Timing in ASM Charts
CS1104-14
Lecture 14: Introdu
Lecture 14: Introduction to

Algorithmic State Machines (ASM)
ASM Charts => Digital System

ASM Charts => Controller
ASM Charts => Architecture/Data Processor
Implementing the Controller

With JK Flip-flops
Decoder + D flip-flops
One Flip-flop per State
Multiplexers
PLA/ROM
CS1104-14
Lecture 14: Introdu
Large Digital Systems
In both combinational and sequential circuit design:

small circuits via gate-level design (truth tables, K maps, etc)
large circuits via block-level design (MSI components, etc.)
However, larger digital systems need more abstract

and systematic design techniques.
One such systematic design method has the following

characteristics:
top-down approach
separation of controller from controlled hardware
develop an overall architecture (at block levels) before
proceeding into the details of hardware.
CS1104-14
Large Digital Syste
Top-Down Approach
Top-down approach is immensely important for large

complex system (whether hardware, software, or
manual systems).
Emphasis on macroscopic view, starting from original

problem and gradually refine it towards solution.
Steps for a top-down design procedure:

Specify the problem clearly (at global/top level without
unnecessary details).
Break the problem into smaller sub-problems.
Repeat the process until subproblems are small enough to
be solved directly (implementable).
CS1104-14
Top-Down Approac
Top-Down Approach
Corresponds to goal-directed approach.

State goal, then find sub-goals to solve main goal.
Repeat until sub-goals are directly solvable.
Pass CS1103
Do Tutorials
Ask questions
CS1104-14
Pass Tests
Practice
Revise
Top-Down Approac
Pass Exam
Sleep well
Controller & Data Processor
Digital systems are typically processors of

information.
They store data through flip-flops, registers and memory, and
process them using combinational circuits like adders,

multipliers, etc.
These processing may pass through complicated sequences.
CS1104-14
Controller & Data P
A digital system consists of two components

A control algorithm (controller) and
An architecture (data processor)
Status condition
Commands
External
command
CS1104-14
Control unit
(Controller)
Input
data
Data
Processor
(Architecture)
Controller & Data P
Output
data
Separation of the controller operations from the data

processing operations
Control operations give commands that direct the data
processing operations to accomplish the desired tasks.

Data processing operations manupulates the data according
to requirements.
A mechanical analogy: Automobile.

Car (data processor): transports people from one location to
another.
Driver (controller): gives instructions to car to achieve
objective.
CS1104-14
Controller & Data P
Flowcharts
Flowcharts: a tool for precise description of

algorithms/procedures.
Specify tasks to perform and their sequencing.
Main symbols:
Operation box: contains tasks/operations to perform.
Decision box: alternative actions based on decisions to be
taken.
Arrows: indicate appropriate sequencing.
CS1104-14
Flowcharts
10
Flowcharts
An operation box is rectangular in shape, and is used

to specify one or more subtasks to be performed. It
has at most one entry point and one exit point.
Sub-task or
operation to
perform
CS1104-14
Flowcharts
11
Flowcharts
A decision box is diamond-shaped. It has one entry

point and multiple (but mutually exclusive) exit points.
choice
option A
CS1104-14
option B
option C
Flowcharts
12
Flowcharts
Sequential flow: simplest type of sequencing; tasks
are done in sequential order.
An example: Eating a 3-course Western meal.

Drink soup
Main course
Eat dessert
Boxes are connected by lines with arrows. Lines without
arrows are sometimes used. In the absence of arrows, the

default flow direction is top-to-bottom and left-to-right.
CS1104-14
Flowcharts
13
Flowcharts
Iteration: some tasks/operations may be

repeatedly/iteratively done.
This is achieved through the loop-back in the

flowchart.
Decision box is used to determine when to terminate

the loop.
CS1104-14
Flowcharts
14
Flowcharts
An example: Eating a Western meal in oriental style.

Drink soup
Main course
no
enough?
yes
Eat dessert
CS1104-14
Flowcharts
15
Flowcharts
Flowcharts
can be used
to implement
complex
decisions.
nice colour
& style?
no
yes
affordable?
no
yes
made in
Europe?
no
poor
insulting
yes
test out
fitting?
acceptable
BFs opinion?
encouraging
reject
CS1104-14
Flowcharts
get BF to buy
16
ASM Charts
Algorithmic State Machine (ASM) Chart is a high-level

flowchart-like notation to specify the hardware
algorithms in digital systems.
Major differences from flowcharts are:

uses 3 types of boxes: state box (similar to operation box),
decision box and conditional box

contains exact (or precise) timing information; flowcharts
impose a relative timing order for the operations.
From the ASM chart it is possible to obtain

the control
the architecture (data processor)
CS1104-14
ASM Charts
17
The state box is rectangular in shape. It has at most

one entry point and one exit point and is used to
specify one or more operations which could be
simultaneously completed in one clock cycle.
state
binary
code
one or more
operations
CS1104-14
Components of ASM
18
The decision box is diamond in shape. It has one

entry point but multiple exit points and is used to
specify a number of alternative paths that can be
followed.
deciding
factors
CS1104-14
deciding
factors
Components of ASM
19

The conditional box is represented by a rectangle with
rounded corners. It always follows a decision box and

contains one or more conditional operations that are
only invoked when the path containing the conditional
box is selected by the decision box.
conditional
operations
CS1104-14
Components of ASM
20
ASM Charts: An Example
An example:
T0
Initial state
A is a register; Ai
stands for ith bit of
the A register.
A = A4A3A2A1
T1
E and F are singlebit flip-flops.
A 0
F 0
A A+ 1
A2
E 0
E 1
A3
T2
1
F 1
CS1104-14
ASM Charts: An Ex
21
Register Operations
Registers are present in the data processor for
storing and processing data. Flip-flops (1-bit

registers) and memories (set of registers) are also
considered as registers.
The register operations are specified in either the
state and/or conditional boxes, and are written in the

form:
destination register function(other registers)
where the LHS contains a destination register (or part of one)
and the RHS is some function over one or more of the
available registers.
CS1104-14
Register Operations
22
Register Operations
Examples of register operations:

AB
A0
AA 1
CS1104-14
Transfer contents of register B into

register A.
Clear register A.
Decrement register A by 1.
Register Operations
23
Precise timing is implicitly present in ASM charts.
Each state box, together with its immediately

following decision and conditional boxes, occurs
within one clock cycle.
A group of boxes which occur within a single clock

cycle is called an ASM block.
CS1104-14
Timing in ASM Char
24

T0
Initial state
1
T1
A 0
F 0
A A+ 1
3 ASM blocks
A2
E 0
E 1
A3
T2
1
F 1
CS1104-14
Timing in ASM Char
25
Operations of ASM can be illustrated through a

timing diagram.
Two factors which must be considered are

operations in an ASM block occur at the same time in one
clock cycle
decision boxes are dependent on the status of the previous
clock cycle (that is, they do not depend on operations of
current block)
CS1104-14
Timing in ASM Char
26
clock
10
11
12 13
states
T0
T0
T1
T1
T1
T1
T1
T1
T1
T2
T0
T0
input
S=0
S=1
A=2
A=3
A=4
register
values
Operations
T0
S=0
A=0
F=0
A=1
A=7
F=1
E=0
A0
F0
A=5 A=6
E=0
AA+1
E0
AA+1
E0
E=1
E=1
AA+1
E1
AA+1
E1
E=0
E=0
E=1
AA+1
E0
AA+1
E0
F1
AA+1
E1
A = A4A3A2A1
CS1104-14
Timing in ASM Char
27

T0
Initial state
clock
states
T0
T0
T1
T1
T1
T1
input
S=0
S=1
A=1
A=2
A=3
E=0
E=0
E=1
register
values
S=0
A=0
F=0
1
T1
A 0
F 0
A0
F0
Operations
A A+ 1
A2
E 0
T2
0
1
F 1
A = A4A3A2A1
CS1104-14
clock
10
11
12 13
states
T1
T1
T1
T2
T0
T0
T0
input
E 1
A3
AA+1
AA+1
E0
E1
AA+1
AA+1
E0
E1
register
values
A=4
A=5 A=6
A=7
E=1
E=0
E=1
F=1
E=0
AA+1
F1
E0
AA+1
AA+1
E0
E1
Operations
Timing in ASM Char
28
ASM Chart => Digital System

ASM chart describes a digital system. From ASM
chart, we may obtain:
Controller logic (via State Table/Diagram)

Architecture/Data Processor
Design of controller is determined from the decision

boxes and the required state transitions.
Design requirements of data processor can be
obtained from the operations specified with the state

and conditional boxes.
CS1104-14
ASM Chart => Digit
29
ASM Chart => Controller
Procedure:
Step 1: Identify all states and assign suitable codes.
Step 2: Draw state diagram.
Step 3: Formulate state table using
State from state boxes

Inputs from decision boxes
Outputs from operations of state/conditional boxes.
Step 4: Obtain state/output equations and draw circuit.
CS1104-14
ASM Chart => Contr
30
ASM Chart => Controller

T0
T2
A 0
F 0
Present
state
G1 G0
A A+ 1
T0 = 00
T1 = 01
T2 = 11
T1
1
T1
Assign codes to states:
T0
Initial state
A2
E 0
E 1
A3
T2
1
F 1
CS1104-14
0
0
0
0
0
1
0
0
1
1
1
1
Next
state
inputs
outputs
A2 A3 G1+ G0+ T0 T1 T2
0
1
X
X
X
X
X
X
0
1
1
X
X
X
X
0
1
X
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
Inputs from conditions in decision boxes.

Outputs = present state of controller.
ASM Chart => Contr
31
ASM Chart => Architecture/Data

Processor
Architecture is more difficult to design than controller.
Nevertheless, it can be deduced from the ASM chart.

In particular, the operations from the ASM chart
determine:
What registers to use
How they can be connected
What operations to support
How these operations are activated.
Guidelines:
always use high-level units
simplest architecture possible.
CS1104-14
ASM Chart => Archi
32

Processor
Various operations are:
Counter incremented (A A + 1) when state = T1.

Counter cleared (A 0) when state = T0 and S = 1.
E is set (E 1) when state = T1 and A2 = 1.
E is cleared (E 0) when state = T1 and A2 = 0.
F is set (F 1) when state = T2.
Deduce:
One 4-bit register A (e.g.: 4-bit synchronous counter with
clear/increment).
Two flip-flops needed for E and F (e.g.: JK flip-flops).
CS1104-14
ASM Chart => Archi
33

Processor
S
A3
start
(A A + 1) when state = T1.

(A 0) when state = T0 and S = 1.
(E 1) when state = T1 and A2 =
1.
T0
Controller
T1
Clk
A2
T2
J
K
J
A4
A3
A2
4-bit syn.
counter A
CS1104-14
A1
count
CP
clear
clock
ASM Chart => Archi
34
Once the state table is obtained, the controller can

be implemented using one of these techniques.
1. Traditional method: With JK flip-flops.

design done at gate level.
suitable for small controllers.
procedure: prepare state table, use K-maps to obtain next-
state/output functions.
2. Decoder + D flip-flops
suitable for moderately large controllers.
procedure: use decoder to obtain individual states; from the
state table, obtain the next-state functions by inspection.
CS1104-14
Implementing the Co
35
3. Multiplexers
a more structured approach to implement controller.
suitable for moderately large controllers.
three level structure:
first level consists of multiplexers that determine the next
state of the register;
second level is a register that holds the present state;
third level has a decoder to provide separate output for each
controller state.
CS1104-14
Implementing the Co
36
4. One flip-flop per state

also known as One-Hot Spot Method of ASM synthesis.
procedure: allocate one flip-flop per state; from state table,
determine the formulae to set each flip-flop; must ensure

that controller is properly initialised.
5. PLA/ROM
highly regular approach.
ROM approach uses a very simple table lookup technique
but suffers from large number of dont care states.

PLA can handle dont care states well but design method is
still at gate-level.
CS1104-14
Implementing the Co
37
Implementing Controller:
With JK Flip-flops
State table
obtained from
ASM chart:
Present
state
G1 G0
0
0
0
0
0
1
0
1
0
1
1
1
inputs
S
0
1
X
X
X
X
A2
X
X
0
1
1
X
A3
X
X
X
0
1
X
Next
state
G1+ G0+
0
0
0
1
0
1
0
1
1
1
0
0
outputs
T0
1
1
0
0
0
0
T1
0
0
1
1
1
0
T2
0
0
0
0
0
1
Corresponding state table using JK flip-flops:

Present
state
G1 G0
0 0
0 0
0 1
0 1
0 1
1 1
CS1104-14
inputs
S A2
0 X
1 X
X 0
X 1
X 1
X X
Next
state
Flip-flop
inputs
A3 G1+ G0+ JG1 KG1 JG0 KG0

X 0
0
0
X
0
X
X 0
1
0
X
1
X
X 0
1
0
X
X
0
0 0
1
0
X
X
0
1 1
1
1
X
X
0
X 0
0
X
1
X
1
Implementing Control
38
Decoder + D Flip-flops
The flip-flop input functions can be obtained directly

from the state table by inspection.
This is because for the D flip-flops, the next state =

flip-flop D input.
Decoder is then used to provide signals to represent

different states.
?
G1
D Q
D Q
G0
2x4
decoder
T0
T1
unused
T2
clock
CS1104-14
Implementing Contro
39
Given the
state table:
Present
state
G1 G0
0
0
0
0
0
1
0
0
1
1
1
1
Next
state
inputs
outputs
A2 A3 G1+ G0+ T0 T1 T2
0
1
X
X
X
X
X
X
0
1
1
X
X
X
X
0
1
X
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
We can directly determine the inputs of the D flip-flops

for G1 and G0.
DG1 = T1.A2.A3
DG0 = T0.S + T1
CS1104-14
Implementing Contro
40
Flip-flop input functions:

DG1 = T1.A2.A3
DG0 = T0.S + T1
Circuit:
A2
A3
G1
D Q
D Q
G0
2x4
decoder
T0
T1
unused
T2
clock
CS1104-14
Implementing Contro
41
Require n flip-flops for n states; each flip-flop

represents one state. (Other methods: n flip-flops
for up to 2n states.)
?
D Q
T0
D Q
T1
:
:
clock
CS1104-14
42
Formulae for next state can be obtained directly

from state table:
1. If there is only one line going into the state, then
formula = input condition ANDed with the previous

state.
2. If there are more than one line, then formula = Ored of
all the conditions found in (1).
CS1104-14
43
State table:
Present
state
Next
state
inputs
S A2 A3
T0
T0
T1
T1
T1
T2
0
1
X
X
X
X
X
X
0
1
1
X
X
X
X
0
1
X
State diagram:
S=0
A2=0
S=1
T0
T1
T1
T1
T2
T0
T0
T1
T2
A2=1,
A3=0
A2=1,
A3=1
Flip-flop input functions:

DT0 = T2 + S'.T0
DT1 = S.T0 + A2'.T1 + A2.A3'.T1 = S.T0 + (A2.A3)'.T1
DT2 = A2.A3.T1
CS1104-14
44
Circuit diagram below. To initialise to state T0, set

flip-flop of T0 to 1 and clear the rest to zero.
preset
A2
A3
DT0 = T2 + S'.T0
DT1 = S.T0 + (A2.A3)'.T1
DT2 = A2.A3.T1
CS1104-14
D Q
T0
D Q
T1
D Q
T2
clock
clear
45
Alternative: Use Q' output for T0, and input function for
T0 is complemented. To initialise, clear all flip-flops to
zero.
D Q
Q'
A2
A3
DT0 = (T2 + S'.T0)'

DT1 = S.T0 + (A2.A3)'.T1
DT2 = A2.A3.T1
CS1104-14
T0
D Q
T1
D Q
T2
clock
clear
46
Implementing Controller:Multiplexers
Purpose of multiplexer is to produce an input to its

corresponding flip-flop equals to the value of the next
state.
The inputs of multiplexers are determined from the

decision boxes and state transitions in the ASM chart.
CS1104-14
47
Example 1: Given
the state table.
Reformat the
state table.
CS1104-14
Present
state
G1 G0
0
0
0
0
0
1
0
1
0
1
1
1
Present
state
inputs
S
0
1
X
X
X
X
Next
state
G1 G0 G1
0 0
0
0 0
0
0 1
0
0 1
0
0 1
1
1 1
0
Next
state
A2 A3 G1+ G0+
X X
0
0
X X
0
1
0 X
0
1
1 0
0
1
1 1
1
1
X X
0
0
G0+
Input
conditions
0
1
1
1
1
0
S'
S
A2'
A2. A3'
A2. A3
1
Multiplexer
inputs
MUX1
MUX0
48
Obtain multiplexer inputs:

Present
state
Next
state
G1 G0 G1
0 0
0
0 0
0
0 1
0
0 1
0
0 1
1
1 1
0
CS1104-14
G0
0
1
1
1
1
0
Input
conditions
S'
S
A2'
A2. A3'
A2. A3
1
Multiplexer
inputs
MUX1
MUX0
A2. A3
A2' + A2. A3' + A2. A3

=1
49
Present
state
Draw circuit:
T0
T1
T2
A2
A3
0
0
0
1 MUX1
2
3
S1 S0
D Q
G1 G0
0 0
0 1
1 1
S1 S0
0
1 MUX0
2
3
Determine next
state of register
CS1104-14
D Q
MUX1
0
A2. A3
0
MUX0
S
1
0
G1
2x4
decoder
S
1
Multiplexer
inputs
G0
T0
T1
T2
clock
Hold present
state
50
Present
state
Example 2:
T0
T1
0
T3
0
0
0
w
1 01
11
T2
CS1104-14
G1 G0 G1
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
1
1
1
00
1
1
Next
state
Present
state
10
y
0
T0
T1
T2
T3
G0
0
1
0
1
0
0
1
1
0
1
Input
conditions
w'
w
x
x'
y'
y.z'
y.z
y'.z
y
y'.z'
Multiplexer
inputs
G1 G0
MUX1
MUX0
0
0
0
w
0
1
x+x'=1
x'
1
0 y.z' + y.z
y.z
=y
1
1
y + y'.z'
y'.z +
= y + z' y'.z' = y'
51
Present
state
T0
T1
T2
T3
y
z'
0
1
y
G1 G0
0 0
0 1
1 0
1 1
Multiplexer
inputs
MUX1
0
1
y
y + z'
0
1 MUX1
2
3
S1 S0
D Q
MUX0
w
x'
y.z
y'
G1
2x4
decoder
y
z
CS1104-14
w
x'
y'
S1 S0
0
1 MUX0
2
3
D Q
G0
T0
T1
T2
T3
clock
52
Implementing Controller: PLA/ROM
Similar to the design using D flip-flops and a decoder.
The only difference is PLA essentially replaces the

decoder and all the gates in the inputs of the flipflops.
External
command
Commands to
architecture
PLA/ROM
Present
state
Next
state
Register to represent states
CS1104-14
Implementing Contr
53
End of segment
CS1103

CS1104 Lecture 14: Introduction to Algorithmic State Machines (ASM

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CS1104 Lecture 14: Introduction to Algorithmic State Machines (ASM

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CS1104 Computer Organization

Aaron Tan Tuck Choy

Lecture 14: Introduction to

Large Digital Systems

Timing in ASM Charts

Lecture 14: Introdu

Lecture 14: Introduction to

ASM Charts => Digital System

Implementing the Controller

Lecture 14: Introdu

Large Digital Systems

In both combinational and sequential circuit design:

However, larger digital systems need more abstract

One such systematic design method has the following

proceeding into the details of hardware.

Large Digital Syste

Top-down approach is immensely important for large

Emphasis on macroscopic view, starting from original

Steps for a top-down design procedure:

Corresponds to goal-directed approach.

Controller & Data Processor

Digital systems are typically processors of

process them using combinational circuits like adders,

Controller & Data P

Controller & Data Processor

A digital system consists of two components

Controller & Data P

Controller & Data Processor

Separation of the controller operations from the data

processing operations to accomplish the desired tasks.

A mechanical analogy: Automobile.

Controller & Data P

Flowcharts: a tool for precise description of

Specify tasks to perform and their sequencing.

An operation box is rectangular in shape, and is used

A decision box is diamond-shaped. It has one entry

An example: Eating a 3-course Western meal.

arrows are sometimes used. In the absence of arrows, the

Iteration: some tasks/operations may be

This is achieved through the loop-back in the

Decision box is used to determine when to terminate

An example: Eating a Western meal in oriental style.

Algorithmic State Machine (ASM) Chart is a high-level

Major differences from flowcharts are:

decision box and conditional box

From the ASM chart it is possible to obtain

Components of ASM Charts

The state box is rectangular in shape. It has at most

Components of ASM Charts

The decision box is diamond in shape. It has one

Components of ASM Charts

rounded corners. It always follows a decision box and

ASM Charts: An Example

E and F are singlebit flip-flops.

storing and processing data. Flip-flops (1-bit

The register operations are specified in either the

state and/or conditional boxes, and are written in the

Examples of register operations:

Transfer contents of register B into

Timing in ASM Charts

Precise timing is implicitly present in ASM charts.

Each state box, together with its immediately