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21-1n-1
Control Unit
Registers
1-2
Program counter PC
Accumulator A
Accumulator B
Accumulator D (D = A cascade B)
Index register X
Index register Y
Stack pointer SP
Conditional code register - CCR
1-3
1-4
address
0
3FFFH
4000H
Data
area
7FFFH
8000H
Program
(Code)
FFFFH
ECE 362 Microprocessor Systems and Interfacing
1-5
Bus Interface
ECE 365-Lee
ECE 365
B _____ D _____
IY _____ PC ____
CCR ______
1-8
1-9
1-10
$1234
1-11
Whats Operand?
LDAB $1234
1-12
1-13
1-14
Operand 1
Operand 2
0 to 2 bytes
0 to 2 bytes
Instruction examples
1-15
It is binary
It is typically read out in hexadecimal
1-16
Computation instructions
arithmetic computations
addition, subtraction, multiplication, division
logical computations
AND, OR, XOR, complement,
load (reading data from memory)
store (writing data to memory)
1-17
1-18
1-19
Immediate
The data is part of the instruction.
Data follows the opcode.
Use # in assembly to indicate immediate.
1-20
LDAA
1-21
PC
86
32
to CPU
Accumulator A
1-22
LDAB
1-23
In program memory
44
86
32
CC
10
24
1-24
1-25
LDD
LDD #$1024
A000
A001
A002
CC ;Opcode
10 ;Operands
24
1-26
Immediate - The data is part of the instruction. Data follows the opcode.
Use # to indicate immediate.
Extended
The memory address of the data is part of the instruction.
An address for data follows the opcode.
68HC12 addresses are 16 bits.
1-27
LDAA $1006
; extended addressing
Corresponding machine code
C000 B6
C001 10
C002 06
What type of addressing is used? _________
Where does the value to be loaded in A come from? ________
What happens if LDAA #$1006 is attempted? ______
How many bytes does it need to access to fetch the instruction?
___________ and to execute the instruction? ___________
How many memory accesses are required for the instruction fetch/execution
if data bus is 16 bits?
ECE 362 Microprocessor Systems and Interfacing
1-28
LDD
$1026
; extended addressing
D000 FC
D001 10
D002 26
The contents of 1026 are loaded in the most significant part of register D
(register A), and the contents of 1027 are loaded in the least significant
part of D (register B).
How many bytes does it need to access to fetch the instruction?
___________ and to execute the instruction? ___________
How many memory accesses are required for the instruction fetch/execution
if data bus is 16 bits (assuming data is aligned in word location)?
1-29
STAA
F000
F001
F002
How many bytes does it need to access to fetch the instruction? ___________
and to execute the instruction? ___________
How many memory accesses are required for the instruction fetch/execution if
data bus is 16 bits (assuming data is aligned in word location)?
1-30
LDAA, LDAB
LDD
LDX, LDY
STAA, STAB
STD
STX, STY
MOVB S,D
MOVW S,D
;Load A or B
;Load D
;Load X or Y
;Store A or B
;Store D
;Store X or Y
(SMem) -> (DMem)
(Smem) -> (Dmem)
1-31
TAB
AB
TBA
BA
XGDX D IX, IX D
XGDY D IY, IY D
TFR S,D S D
LEAX IND (IND) X
LEAY IND (IND) Y
1-32
1-33
Write the mnemonic and machine code that load a hex 3A4 into register
D and then store that value in memory starting at location $850.
1-34
Bits
5-bit signed integers
8-bit signed and unsigned integers
8-bit, 2-digit binary-coded-decimal numbers
9-bit signed integers
16-bit signed and unsigned integers
16-bit effective addresses
32-bit signed and unsigned integers
1-35
1-36
1-37
Examples
ABA ; add B to A
INX ; increment X register by 1
1-38
LDAA
#$3A
1-39
direct mode is for memory page 0 (i.e., first 256 bytes of memory)
Example
LDAA
$3A
LDD $10
STD $0005
1-40
Examples
LDAA
$3A00
LDD $1000
1-41
$30, X
LDD $10, Y
1-42
When adjusted?
either before accessing operand in memory: preor after accessing operand in memory:
postthis is to support various situations (flexibility)
1-43
Pre-autoincrement
Post-autoincrement
use the contents (address) of index register for memory access, and then
increment by the offset amount
Pre-autodecrement
increment the index register by the offset and then use the adjusted value
(address) for memory access
decrement the index register and then use the adjusted value (address)
for memory access
Post-autodecrement
use the contents (address) of index register for memory access, and then
decrement by the offset amount
1-44
Autoincrement
pre-Autoincrement
post-Autoincrement
Autodecrement
pre-Autodecrement
post-Autodecrement
ADAA
LDD 4, Y+
2, +X
ADAA 8, -X
LDD 2, Y-
1-45
What is
Indexed Indirect Addressing with 16-bit Offset?
[$30, X]
LDD [$10, Y]
1-46
[D, X]
LDD [D, Y]
1-47
Examples
BNE
BEQ
1-48
Description
Data location is inherent in instruction
Immediate
Direct
Extended
Relative
Indexed
(constant offset)
Indexed
(pre-decrement)
Indexed
(pre-increment)
Indexed
(post-decrement)
Indexed
(post-increment)
Indexed
(accumulator offset)
Indexed-Indirect
(16-bit offset)
Indexed-Indirect
(D accumulator offset)
Examples
INX
DECB
LDAA #$2C
LDD #$1234
STAA $FC
STD $34
STAB $1234
STX $0848
BNE -$2B
LBEQ $0452
LDD -2,X
JSR 0,Y
STAA 1,-X
MOVW 0,X,2,-X
LDAB 1,+Y
STD 2,+X
STD 2,XLDAA 4,YLDD 2,X+
STAA 1,X+
ADDA B,X
STX D,Y
LDAA [0,Y]
JSR [0,Y]
ADDA [D,X]
JSR [D,Y]
1-49
Some Definitions
Memory Access
Fetch
Read
Data read
Instruction read (fetch)
Write
Data write
reading one instruction (involves decoding)
Execution
1-50
memory
Data
area
1026H
1027H
7FFFH
8000H
8000H
8000H
Program
(Code)
FFFFH
ECE 362 Microprocessor Systems and Interfacing
1-51
LDAA, LDAB
LDD
LDX, LDY
STAA, STAB
STD
STX, STY
;Load A or B
;Load D
;Load X or Y
;Store A or B
;Store D
;Store X or Y
1-52
Example
ADDA
ADDA
ADDA
ADDA
ADDA
10
1000
#10
6,X
[D,X]
1-53
Exercise
load or store
between two memory locations
1-54
1-55
Quiz (cont)
2. Using the table below, disassemble the following machine code. Write
the mnemonics for each instruction.
OPCODE
OPERAND
CC
20
B6
96
40
DC
86
B6
96
25
1-56
Make the dip switches 1,2,3 on the top board at ON position and
the dip switches 4 to 8 on the top board at OFF position
When you fist logged on the computer and using the code
Warrior debugger, go to fileconfigurationload and then
uncheck the box for automatic erase flash
1-57
1-58
1-59
1-60
1-61