Introduction to VLSI

Design
Naveen Bhat,
Teaching assistant
Karnatak university,
dharwad

Few
definations:
Substrate:

Silicon platform on which circuitrary is devoloped.

Photolithography:
Process of transferring pattern on mask to photoresist layer on wafer
surface (pre-pattern the chip)

Etching
Process of permanently removed the unwanted part of design on wafer
surface to get the desired pattern

Diffusion
Process of introducing dophant layer by movement of dophant atoms
from high concentration to low concentration area at high temperature

Ion implantation
Process of introducing dophant layer by bombardment of high energy
dophant ion in high electric field chamber

Oxidation
Process of growing thick or thin SiO2 layer depend on oxide application

Few concepts:

Fabrication yield:
It is a factor that indicates percentage of functional
circuits(sites) on a wafer.
Y=Ng/NtX100

defect density:

Defined as average number of defects per square

cm of the wafer. (limit of perfection).

beading effect:

When a photo resistive material is being sprayed

onto a spinning wafer,except is around the edges of
the wafer. Around the wafer the beads are created.

Electromigration:
When high electrical current is passed, electrons literally
move atoms from one end of an interconnect line,
creating pits called voids.
The atoms pile up at the other end called hillocks.

Solution is to mix the copper.

But resistivity increases.
Another solution,By controlling current density at the
physical design level

lateral doping:

In the fabrication of IC s,during the creation of

active regions , the width and area of the active
regions are defined by the oxide opening, but it
can be observed that n+patterns are largely
gretaer than the openings , due dopant
diffusion called as lateral doping.

Aspect ratio:

Is defined as W/L ratio.

Eulers graph:

Circuit to graph (convert)

1) Vertices are source/Drain connections
2) Edges are transistors

Find p and n Eulerpaths

stick
diagrams

Introduced by Mead & Conway in the 80s

VLSI design aims to translate circuit concepts onto
silicon.
Every line of a conduction material layer is
represented by a line of a distinct color
stick diagrams are a means of capturing
topography and layer information - simple
diagrams.
Used by CAD packages, including Microwind.

CMOS Process Layers

Layer

Color

Well (p,n)

Yellow

Active Area (n+,p+)

Green

Select (p+,n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Contact To Poly

Black

Contact To Diffusion

Black

Via

Black

Representation

Stick Diagrams

Logic Gates Design

Design rules:

Interface between designer and process engineer

Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

Intra-Layer Design Rules

SamePotential
Well
10

0
or
6

9
Polysilicon
2

Active
3

2
Select

DifferentPotential

Metal1
Contact
orVia
Hole

2
2

3
Metal2
3

First step..
VDD

Vin
Vout

GND

NANd 2:

NOR2: