Laser on silicon

courtesy: Blas Garrido

http://silicon-photonics.ief.u-psud.fr/

Laurent Vivien

Laser on silicon
Group IV materials . Indirect bandgap materials.
What are the potentialities of such materials?
Erbium doped silicon nanocrystals
Strained germanium to go towards a pseudo direct gap
material
Ge/SiGe heterostructures

III-V SC on silicon
Is it a CMOS compatible technology?
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Laurent Vivien

Germanium laser

Demonstration of optical gain in strained Ge

Demonstration of electro-luminescence
Demonstration of the first Ge laser
The first Ge laser; J. Liu, X. Sun, L.C. Kimerling, J. Michel : Presentation at Group IV photonics San Francisco (September 2009).

http://silicon-photonics.ief.u-psud.fr/

Laurent Vivien

Gemanium laser

http://silicon-photonics.ief.u-psud.fr/

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III-V on silicon
Numerous works did and to do

J. Van Campenhout et al., Optics Express,15(11),p.6744-6749(2007)

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Laurent Vivien

Option beta Use wire-bonding to connect chips

Not a waferscale approach

Not compatible with micro-electronics packaging

http://silicon-photonics.ief.u-psud.fr/

Laurent Vivien

Photonics-electronics integration

Transistors

Photonics

Front-end
fabrication

Very low
parasitics
Custom SOI,
specific libraries
process cohttp://silicon-photonics.ief.u-psud.fr/

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Front-end approach

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CMOS front-end monolithic nanophotonics

integration IBM approach

Nanophotonics sharing Si layer with FET body

Advantages:

Deeply scaled Nanophotonics

Most dense integration with CMOS
Ultra-low power optical interconnects
Same mask set, standard processing
Same design environment (e.g. Cadence)
Same EDA tools and design flow
Possible in-line system-level testing
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Laurent Vivien

Photonics-electronics integration

Photonics

Transistors

Photonics

Front-end
fabrication

Transistors

Back-end
fabrication

On top of CMOS or
Very low parasitics
Custom SOI, specific in metal layers

Serial process
libraries
Compound yield
process co Thermal budget <
integration
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Laurent Vivien

http://silicon-photonics.ief.u-psud.fr/

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Laurent Vivien

Photonics-electronics integration

Photonics

Photonics

Transistors

Photonics

Transistors
Transistors

Front-end
fabrication

Very low parasitics

Custom SOI,
specific libraries
process cointegration
http://silicon-photonics.ief.u-psud.fr/

Back-end
fabrication

or

3D integration
Separate processes
No change in CMOS
On top of CMOS
Front-End
in metal layers
No thermal budget!
Serial process
Other layers: MEMS,
Compound yield
antennas
Thermal budget < Higher (but reasonable)
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3D integration
Pad

FC

AWG

InP source
Modulator

Ge PD

3D integration
Not depending on the
specific node used to
produce the electronic
wafer

CMOS
wafer
transistors

Si rib waveguide
Germanium

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metal interconnects

AWG on CMOS

Germanium PD

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Flip grating coupler

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Conclusion
Photonic links may replace copper links, even for very
short distances
Integration on silicon is key
To reach competitive cost
To reduce size and power consumption while scaling up
bandwidth

A full design, fabrication and integration chain is under

construction
High performance building blocks demonstrated
Versatile photonics-electronics integration process

Complex circuits are under development

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Laurent Vivien

Main challenges
Silicon photonics is still in its infancy and is facing
several challenges:
Automated design flow
Laser: yield,Keys
reliability,
temperature
for development:
Integrated, hybrid assembly or external ?
Reliability at wafer scale
Modulator: footprint,
driving
voltage,
power consumption
Driving
voltage
of modulator
Power consumption
Process integration
Integration cost
Integration of complex
circuits: thermal, electrical, photonic
Packaging
crosstalk/feedback
Photonic-electronic integration scheme
Front end, 3D wafer-wafer integration, 3D chip to wafer
Packaging: RF, optical, thermal management
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Laurent Vivien