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Digital Design Flow

Digital Design Flow begins with specification of the


design at various levels of abstraction.

Design entry phase: Specification of design as a


mixture of behavioral
Verilog code, instantiation of Verilog modules, and
bus and wire assignments

Verilog Digital System Design


Z. Navabi, 2006

Digital Design Flow

FPLD Design Flow


Verilog Digital System Design
Z. Navabi, 2006

Digital Design Flow

Design
Entry
Phase

FPLD Design Flow

Verilog Digital System Design


Z. Navabi, 2006

Digital Design Flow

Presynthesis verification: Generating testbenches for


verification of the design and later for verifying the
synthesis output

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Digital Design Flow

Presynthesis
Verification

FPLD Design Flow


(Continued)

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Digital Design Flow

Synthesis process: Translating the design into actual


hardware of a target device (FPLD, ASIC or custom
IC)

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Z. Navabi, 2006

Digital Design Flow

Synthesis
Process

FPLD Design Flow


(Continued)

Verilog Digital System Design


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Digital Design Flow

Postsynthesis simulation: Testing the behavioral


model of the design and its hardware model by using
presynthesis test data

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Digital Design Flow

Postsynthesi
s
Verification

FPLD Design Flow (Continued)

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Digital Design Flow

Digital Design Flow ends with generating netlist for


an application specific integrated circuits (ASIC),
layout for a custom IC, or a program for a
programmable logic devices (PLD)

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Digital Design Flow

FPLD Design Flow (Continued)

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Digital Design Flow


Digital Design
Flow
Design Entry

Testbench in Verilog

Design Validation

Compilation
and Synthesis

Postsynthesis
Simulation

Timing
Analysis

Hardware
Generation
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Verilog HDL

A language that can be understood by:


System Designers
RT Level Designers,
Test Engineers
Simulators
Synthesis Tools
Machines
Has become an IEEE standard

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The Verilog Language

The Verilog HDL satisfies all requirements for design


and synthesis of digital systems:

Supports hierarchical description of hardware


from system to gate or even switch level.
Has strong support at all levels for timing
specification and violation detection.
A hardware component is described by the
module_declaration language construct in it.

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The Verilog Language

The Verilog HDL satisfies all requirements for design


and synthesis of digital systems (Continued):

Description of a module specifies a components


input and output list as well as internal
component busses and registers within a module,
concurrent assignments, component
instantiations, and procedural blocks can be used
to describe a hardware component.
Several modules can hierarchically be instantiated
to form other hardware structure.
Simulation environments provide graphical frontend programs and waveform editing and display
tools.
Synthesis tools are based on a subset of Verilog.

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Elements of Verilog

We discuss basic constructs of Verilog language for


describing a hardware module.

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Elements of Verilog
Hardware
Modules
Primitive
Instantiations

Assign
Statements

Condition
Expression

Procedural
Blocks

Module
Instantiations
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Hardware Modules
Hardware
Hardware
Modules
Modules
Primitive
Instantiations

Assign
Statements

Condition
Expression

Procedural
Blocks

Module
Instantiations
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Hardware Modules

module :
The Main
Compone
nt of
Verilog

Keywor
d
module

module module-name
Variables,
List of ports;
wires, and
Declarations
module
parameters
...
are declared.
Functional specification
of module
...
Keyword
endmodule
endmod
ule

Module Specifications

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Hardware Modules

There is more than one way to describe a Module in


Verilog.
May correspond to descriptions at various levels of
abstraction or to various levels of detail of the
functionality of a module.
We show a small example and several alternative ways
to describe it in Verilog.

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Primitive Instantiations
Hardware
Modules
Primitive
Primitive
Instantiations

Assign
Statements

Condition
Expression

Procedural
Blocks

Module
Instantiations
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Primitive Instantiations
Logic
Gates
called
Primitive
s

A Multiplexer Using Basic Logic Gates

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Primitive Instantiations
module MultiplexerA (input a, b, s, output w);
wire a_sel, b_sel, s_bar;
not U1 (s_bar, s);
Instantiatio
and U2 (a_sel, a, s_bar);
n
and U3 (b_sel, b, s);
of
or
U4 (w, a_sel, b_sel);
Primitives
endmodule

Primitive Instantiations

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Assign Statements
Hardware
Modules
Primitive
Instantiations

Assign
Assign
Statements
Statements

Condition
Expression

Procedural
Blocks

Module
Instantiations
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Assign Statements
Continuously
drives w with
the
right hand
side
expression

module MultiplexerB (input a, b, s, output w);


assign w = (a & ~s) | (b & s);
endmodule

Assign Statement and Boolean

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Using
Boolean
expressions
to describe
the logic

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Condition Expression
Hardware
Modules
Primitive
Instantiations

Assign
Statements

Condition
Condition
Expression

Procedural
Blocks

Module
Instantiations
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Condition Expression
Can be used
when the
operation of a
unit is too
complex to be
described by
Boolean
module MultiplexerC (input a, b, s, output w);
expressions
assign w = s ? b : a;

endmodule

Assign Statement and Condition Operator

Useful in
describing a
behavior in a
very compact
way
Verilog Digital System Design
Z. Navabi, 2006

Very Effective
in describing
complex
functionalities

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Procedural Blocks
Hardware
Modules
Primitive
Instantiations

Assign
Statements

Condition
Expression

Procedural
Procedural
Blocks

Module
Instantiations
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Procedural Blocks
always
stateme
nt

Sensitivity
list

module MultiplexerD (input a, b, s, output w);


reg w;
always @(a, b, s) begin
if (s) w = b;
else w = a;
Can be used when
end
if-else
the operation of a
statemen
endmodule
t

Procedural Statement

Verilog Digital System Design


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unit is too
complex to be
described by
Boolean or
conditional
expressions
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Module Instantiations
Hardware
Modules
Primitive
Instantiations

Assign
Statements

Condition
Expression

Procedural
Blocks

Module
Module
Instantiations
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Module Instantiations
module ANDOR (input i1, i2, i3, i4, output ANDOR
y);
assign y = (i1 & i2) | (i3 & i4);
module is
endmodule
defined
//
module MultiplexerE (input a, b, s, output
w);
wire s_bar;
not U1 (s_bar, s);
ANDOR U2 (a, s_bar, s, b, w);
ANDOR
endmodule
module is
instantiated
Module Instantiation

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Module Instantiations

Multiplexer Using ANDOR

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Component Description
in Verilog
Component
Description

Data
Controllers
Components

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Data Components
Component
Description

Data
Data
Controllers
Components
Components

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Data Components
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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Multiplexer
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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Multiplexer
Defines a Time Unit of
1 ns and Time
Precision of 100 ps.

`timescale 1ns/100ps
module Mux8 (input
output
assign #6 bus1 =
endmodule

sel, input [7:0] data1, data0,


[7:0] bus1);
sel ? data1 : data0;

A 6-ns Delay
is specified for
all values
assigned to
bus1

A 6-ns
Octal 2-to-1 MUX

Verilog Digital System Design


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Selects its 8-bit


data0 or data1
input depending
on its
sel input.
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Flip-Flop
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
Verilog Digital System Design
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The Body of
always
statement is
Synchrono
executed at
us reset
the negative
input
edge of the clk
signal 1ns/100ps
`timescale

Flip-Flop

Flip-Flop
triggers on
the falling
edge of clk
Input

module Flop (reset, din, clk, qout);


input reset, din, clk;
A Signal
output qout;
declared as a
reg to be
reg qout;
capable of
always @(negedge clk) begin
holding its
if (reset) qout <= #8 1'b0;
values between
else qout <= #8 din;
clock edges
end
A Nonendmodule

Flip-Flop Description

An 8ns
Delay

blocking
Assignment

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Counter
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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A 4-bit
modulo-16
Counter

Counter
4-bit
Register

`timescale 1ns/100ps
module Counter4 (input reset, clk,
output [3:0] count);
Constant
reg [3:0] count;
Definition
always @(negedge clk) begin
if (reset) count <= #3 4'b00_00;
else count <= #5 count + 1;
end
When count
endmodule
reaches

1111,
the next
count taken
is 10000

Counter Verilog Code

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Full-Adder
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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Full-Adder
All Changes
Occur after
5 ns

A
combination
al
circuit

`timescale 1ns/100ps
module fulladder (input a, b, cin, output sum, cout);
assign #5 sum = a ^ b ^ cin;
assign #3 cout = (a & b)|(a & cin)|(b & cin);
endmodule

Full-Adder Verilog Code

One delay for


every output:
tPLH and
tPHL

All Changes
Occur after
3 ns

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Shift-Register
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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Shift-Register

An 8-bit
Universal
Shift
Register

2 Mode
inputs
m[1:0] form 1ns/100ps
`timescale
a
2-bitShiftRegister8
module
number
(input sl, sr, clk, Case
inputStatement
[7:0] ParIn,
input [1:0] m, outputWith
reg 4[7:0]
case- ParOut);
alternatives
default Value
always @(negedge clk) and
begin

case (m)
m=0 : Does
0: ParOut <= ParOut;
Nothing
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr};
m=1,2: Shifts
3: ParOut <= ParIn;
Right and
Left
default: ParOut <= 8'bX;
endcase
m=3 : Loads its
end
Parallel input into
endmodule
the register
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Shift-Register
`timescale 1ns/100ps
(Continued)
module ShiftRegister8
(input sl, sr, clk, input [7:0] ParIn,
input [1:0] m, output reg [7:0] ParOut);

Shift Right:
The SL
input is
concatenate
d to the left
of ParOut

always @(negedge clk) begin


case (m)
0: ParOut <= ParOut;
1: ParOut <= {sl, ParOut [7:1]};
2: ParOut <= {ParOut [6:0], sr};
3: ParOut <= ParIn;
default: ParOut <= 8'bX;
Shifting the
endcase
ParOut to
end
the left
endmodule
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ALU
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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ALU
`timescale 1ns/100ps
module ALU8 (input [7:0] left, right,
input [1:0] mode,
output reg [7:0] ALUout);
always @(left, right, mode) begin
case (mode)
0: ALUout = left + right;
1: ALUout = left - right;
2: ALUout = left & right;
3: ALUout = left | right;
default: ALUout = 8'bX;
endcase
end
endmodule

2-bit mode
Input to
select one of
its 4
functions
Add
Subtrac
t
AND
OR

An 8-bit ALU
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ALU (Continued)

The
Declaration of
`timescale 1ns/100ps
ALUout both as
output and reg:
Because of
module ALU8 (input [7:0] left, right,
assigning it
input [1:0] mode,
within a
output reg [7:0] ALUout);
Procedural
always @(left, right, mode) begin
Blocking Block
case (mode)
Assignme
0: ALUout = left + right;
nts

1: ALUout = left - right;


2: ALUout = left & right;
3: ALUout = left | right;
default: ALUout = 8'bX;
endcase
end
endmodule

An 8-bit ALU
Verilog Digital System Design
Z. Navabi, 2006

default
alternative
puts all Xs on
ALUOut
if mode contains
anything but 1s
and 0s
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Interconnections
Data
Components
Multiplexer

Flip-Flop

Counter

Full-Adder

Shift-Register

ALU

Interconnections
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Interconnections

Mux8 and
ALU examples
forming a
Partial
Hardware

Partial Hardware Using MUX8 and ALU

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Interconnections
A Set of
Instantiation
parenthesis
of ALU8 and
enclose port
MUX8
connections to
the
ALU8 U1 ( .left(Inbus), .right(ABinput), instantiated
modules
.mode(function), .ALUout(Outbus) );

Mux8 U2 ( .sel(select_source), .data1(Aside),


.data0(Bside), .bus1 (ABinput));
Verilog
u1
and u2
: of The Partial Hardware Example
Code
Instance
Names

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Interconnections
The actual
ports
of the
instantiated
components
are excluded

An Alternative
format of port
connection

ALU8 U1 ( Inbus, ABinput, function, Outbus );


Mux8 U2 ( select_source, Aside, Bside, ABinput );

Ordered Port Connection

The list of local


signals in the
same order as
their connecting
ports

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Controllers
Component
Description

Data
Controllers
Controllers
Components

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Controllers

Controller Outline

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Controllers

Controller:
Is wired into data part to control its flow of data.
The inputs to it controller determine its next states and
outputs.
Monitors its inputs and makes decisions as to when and what
output signals to assert.
Keeps the history of circuit data by switching to appropriate
states.
Two examples to illustrate the features of Verilog for describing
state machines:
Synchronizer
Sequence Detector

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Controllers
Controllers

Sequence
Synchronizer
Detector

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Synchronizer
Controllers

Synthesizer
Synchronizer

Sequence
Detector

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Synchronizer

Synchronizing adata

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Synchronizer
`timescale 1ns/100ps
module Synchronizer (input clk, adata,
output reg synched);
always @(posedge clk)
if (adata == 0) synched <= 0;
else synched <= 1;
endmodule

A Simple Synchronization Circuit

Verilog Digital System Design


Z. Navabi, 2006

If a 1 is
Detected on
adata on the
rising edge of
clock, synched
becomes 1 and
remains 1
for at least one
clock period
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Sequence Detector
Controllers

Synthesizer

Sequence
Sequence
Detector
Detector

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Sequence Detector
When the
sequence
is detected, the
w Output
becomes 1 and
stays 1 for a
complete clock
cycle

Searches
on
its a
input
for the
110
Sequence

State Machine Description

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Sequence Detector
A Moore
Machine
Sequence
Detector

States are
named:
s0 , s1 , s2 ,
s3

Initi
al
Stat
e

Sequence Detector State Machine

Verilog Digital System Design


Z. Navabi, 2006

The State in
which the 110
sequence is
detected.

It Takes at
least
3 clock
periods to get
to the s3 state

63

Sequence Detector
module Detector110 (input a, clk, reset, output w);
parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
reg [1:0] current;
always @(posedge clk) begin
if (reset) current = s0;
else
case (current)
s0: if (a) current <= s1;
s1: if (a) current <= s2;
s2: if (a) current <= s2;
s3: if (a) current <= s1;
endcase
end

else
else
else
else

current
current
current
current

<=
<=
<=
<=

s0;
s0;
s3;
s0;

assign w = (current == s3) ? 1 : 0;


endmodule

Verilog Code for

110 Detector
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64

Behavioral
Sequence Detector
Description of
the State
Machine

module Detector110 (input a, clk, reset, output w);


parameter [1:0] s0=2'b00, s1=2'b01, s2=2'b10,
s3=2'b11;
reg [1:0] current;

A 2-bit
Register

always @(posedge clk) begin


if (reset) current = s0;
else
...........................
...........................

Verilog Code for

Parameter
declaration
defines constants
s0, s1, s2, s3

110 Detector

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Sequence Detector
...........................
...........................
always @(posedge clk) begin
if (reset) current = s0;
else
At thecase (current)
s0: if (a) current <= s1; else
Absence
s1: if (a) current <= s2; else
of a 1 on
reset s2: if (a) current <= s2; else
s3: if (a) current <= s1; else
endcase
end

Verilog Code for

110 Detector

Verilog Digital System Design


Z. Navabi, 2006

if-else
statement
checks for
reset

current
current
current
current

<=
<=
<=
<=

s0;
s0;
s3;
s0;

The 4 Casealternatives
each correspond
to a state of state
machine
66

Sequence Detector

State Transitions on Corresponding Verilog Code

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Sequence Detector
Outside of
the always
Block:
A
end
combination
............................al circuit

............................
assign w = (current == s3) ? 1 : 0;
endmodule

Verilog Code for

110 Detector

Verilog Digital System Design


Z. Navabi, 2006

Assigns a 1 to
w output when
Machine
Reaches to s3
State

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