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Microprocessors 1-1
Microprocessors 1-2
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Microprocessors 1-3
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Microprocessors 1-4
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Microprocessors 1-5
CPU
I/O
Port
RAM ROM
Serial
Timer COM
Port
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A single chip
Microcontroller
Microprocessors 1-6
Block Diagram
External Interrupts
Interrupt
Control
Timer 1
Timer 2
4k
ROM
128 bytes
RAM
Bus
Control
4 I/O Ports
CPU
OSC
P0 P2 P1
Addr/Data
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P3
Serial
TXD RXD
Microprocessors 1-7
Microprocessors 1-8
Embedded System
(8051 Application)
task only
There is only one application software that is typically burned into ROM
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Microprocessors 1-9
Microprocessors 1-10
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Microprocessors 1-11
8051
Schematic
Pin out
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Microprocessors 1-12
8051
Foot Print
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(INT0)P3.2
(INT1)P3.3
(T0)P3.4
(T1)P3.5
(WR)P3.6
(RD)P3.7
XTAL2
XTAL1
GND
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8051
(8031)
(8751)
(8951)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vcc
P0.0(AD0
)P0.1(AD1)
P0.2(AD2
) 0.3(AD3)
P
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14
)P2.5(A13
)P2.4(A12
)P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
Microprocessors 1-13
Microprocessors 1-14
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Microprocessors 1-15
IMPORTANT PINS
PSEN (out):
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Microprocessors 1-16
Pins of 8051
Vcc pin 40
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND pin 20 ground
XTAL1 and XTAL2 pins 19,18
These 2 pins provide external clock.
Way 1 using a quartz crystal oscillator
Way 2 using a TTL oscillator
Example 4-1 shows the relationship
between XTAL and the machine cycle.
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Microprocessors 1-17
Machine cycle
Solution:
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Microprocessors 1-18
Pins of 8051
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Microprocessors 1-19
Pins of 8051
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Microprocessors 1-20
Pins of 8051
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Microprocessors 1-21
Address Multiplexing
for External Memory
Figure 27
Multiplexi
ng the
address
(low-byte)
and data
bus
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Microprocessors 1-22
Address Multiplexing
for External Memory
Figure 28
Accessing
external
code
memory
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Microprocessors 1-23
Accessing External
Data Memory
Figure
2-11
Interfac
e to 1K
RAM
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Microprocessors 1-24
74LS373
G
D
OE
CS
A0
A7
D0
D7
EA
P2.0
A8
P2.7
A15
8051
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ROM
Microprocessors 1-25
WR
RD
74LS373
G
D
CS
A0
A7
D0
D7
EA
P2.0
A8
P2.7
A15
8051
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RAM
Microprocessors 1-26
WR
RD
74LS373
G
D
CS
A0
A7
D0
D7
EA
P2.0
A8
P2.7
A15
8051
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RAM
Microprocessors 1-27
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Microprocessors 1-28
On-Chip Memory
Internal RAM
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Microprocessors 1-29
Registers
1F
Bank 3
18
17
Bank 2
10
0F
Bank 1
08
07
06
05
04
03
02
01
00
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R7
R6
R5
R4
R3
R2
R1
R0
Bank 0
Microprocessors 1-30
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Microprocessors 1-31
Register Banks
Active bank selected by PSW [RS1,RS0] bit
Permits fast context switching in interrupt
service routines (ISR).
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Microprocessors 1-32
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Microprocessors 1-33
Used in assembler
instructions
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Microprocessors 1-34
Registers
A
B
R0
DPTR
DPH
DPL
R1
R2
PC
PC
R3
R4
R5
R6
R7
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Microprocessors 1-35
The 8051
Assembly Language
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Microprocessors 1-36
Overview
Data transfer instructions
Addressing modes
Data processing (arithmetic and logic)
Program flow instructions
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Microprocessors 1-37
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Microprocessors 1-38
Addressing Modes
Immediate Mode specify data by its value
mov A, #0
mov R4, #11h
mov B, #11
mov DPTR,#7521h
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Microprocessors 1-39
Addressing Modes
Immediate Mode continue
MOV DPTR,#7521h
MOV DPL,#21H
MOV DPH, #75
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Microprocessors 1-40
Addressing Modes
Register Addressing either source or destination is one of
CPU register
MOV R0,A
MOV
ADD
ADD
MOV
MOV
MOV
A,R7
A,R4
A,R7
DPTR,#25F5H
R5,DPL
R,DPH
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Microprocessors 1-41
Addressing Modes
Direct Mode specify data by its 8-bit address
a, 70h
R0,40h
56h,a
0D0h,a
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Microprocessors 1-42
Addressing Modes
Register Indirect the address of the source or
destination is specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0
mov r0, #0x3C
mov @r0, #3
; dptr 9000h
; a M[9000]
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Microprocessors 1-43
Addressing Modes
Register Indexed Mode source or destination address is
the sum of the base address and the
accumulator(Index)
Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr
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;a M[4005]
Microprocessors 1-44
Acc Register
A register can be accessed by direct and register
mode
This 3 instruction has same function with different
code
0703 E500
0705 8500E0
0708 8500E0
mov a,00h
mov acc,00h
mov 0e0h,00h
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mov a,r1
mov acc,r1
mov 0e0h,r1
Microprocessors 1-45
Exchange Instructions
two way data transfer
XCH a, 30h
XCH a, R0
XCH a, @R0
XCHD a, R0
;
;
;
;
a M[30]
a R0
a M[R0]
exchange digit
a[7..4] a[3..0]
R0[7..4] R0[3..0]
Only 4 bits exchanged
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Microprocessors 1-46
Data Processing
Instructions
Arithmetic Instructions
Logic Instructions
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Microprocessors 1-47
Arithmetic Instructions
Add
Subtract
Increment
Decrement
Multiply
Divide
Decimal adjust
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Microprocessors 1-48
Arithmetic Instructions
Mnemonic
Description
ADD A, byte
ADDC A, byte
SUBB A, byte
INC A
increment A
INC byte
INC DPTR
DEC A
decrement accumulator
DEC byte
decrement byte
MUL AB
DIV AB
DA A
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Microprocessors 1-49
ADD Instructions
add a, byte
; a a + byte
addc a, byte
; a a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6, or
visa versa.
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Microprocessors 1-50
ADD Examples
mov a, #3Fh
add a, #D3h
0011 1111
1101 0011
0001 0010
C = 1
AC = 1
OV = 0
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Microprocessors 1-51
clear
rotate left
rotate left through Carry
rotate right
rotate right through Carry
swap accumulator nibbles
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Microprocessors 1-52
Rotate
Rotate instructions operate only on
RL a
RR a
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Microprocessors 1-53
Why Subroutines?
Subroutines allow us to have "structured" assembly
language programs.
This is useful for breaking a large design into
manageable parts.
It saves code space when subroutines can be called
many times in the same program.
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Microprocessors 1-54
Interrupt Sources
Original 8051 has 5 sources of interrupts
Timer 0 overflow
Timer 1 overflow
External Interrupt 0
External Interrupt 1
Serial Port events (buffer full, buffer empty, etc)
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Microprocessors 1-55
Interrupt Process
If interrupt event occurs AND interrupt flag for
that event is enabled, AND interrupts are
enabled, then:
1. Current PC is pushed on stack.
2. Program execution continues at the interrupt
vector address for that interrupt.
3. When a RETI instruction is encountered, the
PC is popped from the stack and program
execution resumes where it left off.
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Microprocessors 1-56
Interrupt Priorities
What if two interrupt sources interrupt at the same
time?
The interrupt with the highest PRIORITY gets serviced
first.
All interrupts have a default priority order.
Priority can also be set to high or low.
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Microprocessors 1-57
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Microprocessors 1-58