Logic and Computer Design Fundamentals

Chapter 8 Memory Basics

Charles Kime & Thomas Kaminski

2008 Pearson Education, Inc.
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Overview
Memory definitions
Random Access Memory (RAM)
Static RAM (SRAM) integrated circuits
Cells and slices
Cell arrays and coincident selection

Arrays of SRAM integrated circuits

Dynamic RAM (DRAM) integrated circuits
DRAM Types
Synchronous (SDRAM)
Double-Data Rate (DDR SRAM)
RAMBUS DRAM (RDRAM)

Arrays of DRAM integrated circuits

Chapter 8 2

Memory Definitions
Memory A collection of storage cells together with
the necessary circuits to transfer information to and
from them.
Memory Organization the basic architectural
structure of a memory in terms of how data is accessed.
Random Access Memory (RAM) a memory
organized such that data can be transferred to or from
any cell (or collection of cells) in a time that is not
dependent upon the particular cell selected.
Memory Address A vector of bits that identifies a
particular memory element (or collection of elements).

Chapter 8 3

Memory Definitions (Continued)

Typical data elements are:
bit a single binary digit
byte a collection of eight bits accessed together
word a collection of binary bits whose size is a
typical unit of access for the memory. It is typically a
power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4
bytes, 8 bytes, etc.)

Memory Data a bit or a collection of bits to be

stored into or accessed from memory cells.
Memory Operations operations on memory
data supported by the memory unit. Typically,
read and write operations over some data
element (bit, byte, word, etc.).
Chapter 8 4

Memory Organization
Organized as an indexed array of words. Value of the
index for each word is the memory address.
Often organized to fit the needs of a particular
computer architecture. Some historically significant
computer architectures and their associated memory
organization:
Digital Equipment Corporation PDP-8 used a 12-bit address
to address 4096 12-bit words.
IBM 360 used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
Intel 8080 (8-bit predecessor to the 8086 and the current
Intel processors) used a 16-bit address to address 65,536 8-bit
bytes.
Chapter 8 5

Memory Block Diagram

A basic memory system is
shown here:
k address lines are
k Address
decoded to address 2k Lines
words of memory.
Read
Each word is n bits.
Write
Read and Write are single
control lines defining the
simplest of memory
operations.

n Data Input Lines

n

k
1

Memory
Unit
2k Words
n Bits per Word

1
n

n Data Output Lin

Chapter 8 6

Memory Organization Example

Example memory
contents:
A memory with 3
address bits & 8
data bits has:
k = 3 and n = 8 so
23 = 8 addresses
labeled 0 to 7.
23 = 8 words of 8-bit
data

Memory Address
Binary Decimal
000
001
010
011
100
101
11 0
111

0
1
2
3
4
5
6
7

Memory
Content
10001111
11111111
10110001
00000000
10111001
10000110
00110011
11001100

Chapter 8 7

Basic Memory Operations

Memory operations require the following:
Data data written to, or read from, memory as
required by the operation.
Address specifies the memory location to operate
on. The address lines carry this information into
the memory. Typically: n bits specify locations of 2 n
words.
An operation Information sent to the memory and
interpreted as control information which specifies
the type of operation to be performed. Typical
operations are READ and WRITE. Others are
READ followed by WRITE and a variety of
operations associated with delivering blocks of data.
Operation signals may also specify timing info.
Chapter 8 8

Basic Memory Operations (continued)

Read Memory an operation that reads a data value
stored in memory:
Place a valid address on the address lines.
Wait for the read data to become stable.

Write Memory an operation that writes a data value to

memory:
Place a valid address on the address lines and valid data on the
data lines.
Toggle the memory write control line

Sometimes the read or write enable line is defined as a

clock with precise timing information (e.g. Read Clock,
Write Strobe).
Otherwise, it is just an interface signal.
Sometimes memory must acknowledge that it has completed the
operation.
Chapter 8 9

Memory Operation Timing

Most basic memories are asynchronous
Storage in latches or storage of electrical charge
No clock

Controlled by control inputs and address

Timing of signal changes and data observation is critical to the
operation
Read timing:
Clock
Address

20 ns
T1

T2

T3

T4

T1

Address valid

Memory
enable
Read/
Write
Data
output

Data valid
65 ns
Read cycle

Chapter 8 10

Memory Operation Timing

Write timing:
Clock
Address

20 ns
T1

T2

T3

T4

T1

Address valid

Memory
enable
Read/
Write
Data
input

Data valid
75 ns
Write cycle

Critical times measured with respect to edges of write pulse (1-0-1):

Address must be established at least a specified time before 1-0 and held for at
least a specified time after 0-1 to avoid disturbing stored contents of other
addresses
Data must be established at least a specified time before 0-1 and held for at
least a specified time after 0-1 to write correctly
Chapter 8 11

RAM Integrated Circuits

Types of random access memory
Static information stored in latches
Dynamic information stored as electrical charges
on capacitors
Charge leaks off
Periodic refresh of charge required

Dependence on Power Supply

Volatile loses stored information when power
turned off
Non-volatile retains information when power
turned off
Chapter 8 12

Static RAM Cell

Array of storage cells used to implement static
RAM
Select
Storage Cell
SR Latch
Select input for
control
Dual Rail Data
Inputs B and B
Dual Rail Data
Outputs C and C

Q
RAM cell

Chapter 8 13

Static RAM Bit Slice

Represents all circuitry that is required for 2n
1-bit words
Select

Word
select
0

Multiple RAM cells

Control Lines:
Word select i
one for each word
Read / Write
Bit Select

Word
select
0

RA M cell

RA M cell

Word
select
1
RA M cell

Select

Word
select
2n 2 1

Data Lines:
Data in
Data out

Word
select
2n 2 1

RA M cell

X
RA M cell

Read/Write
logic

Data in

Data in
Data out
Read/
Bit
Write
select
(b) Symbol

Write logic
Read/
Write

Bit
select

Read logic
(a) Logic diagram

Data out

Chapter 8 14

2n-Word 1-Bit RAM IC

To build a RAM IC
from a RAM slice,
we need:
Decoder decodes
the n address lines to
2n word select lines

A3

A3

A2

A2

A1

A1

A0

16 x 1
RAM

Data
output

Data
input

A 3-state buffer
Read/
Write
on the data output Memory
permits RAM ICs to enable
be combined into a
RAM with c 2n words

A0

Word select
4-to-16
Decoder 0
1
23
2
RAM cell
2
3
2
4
1
5
2
6
RAM cell
0
7
2
8
9
10
11
12
13
14
15
RAM cell

Read/Write
logic

(a) Symbol
Data input

Data in
Data out
Read/ Bit
Write select

Data
output

Read/Write
Chip select

(b) Block diagram

Chapter 8 15

Cell Arrays and Coincident Selection

Memory arrays can be very large
Large decoders
Large fanouts for the bit lines
The decoder size and fanouts can be reduced by
approximately n by using a coincident selection in
a 2-dimensional array
Uses two decoders, one for words and one for bits
Word select becomes Row select
Bit select becomes Column select

See next slide for example

A3 and A2 used for Row select
A1 and A0 for Column select
Chapter 8 16

Cell Arrays and Coincident Selection

A3

Row decoder
2-to-4
Decoder 0
21

A2

20

RAM cell
0

RAM cell
1

RAM cell
2

RAM cell
3

Row RAM cell

4
select

RAM cell
5

RAM cell
6

RAM cell
7

RAM cell
8

RAM cell
9

RAM cell
10

RAM cell
11

RAM cell
12

RAM cell
13

RAM cell
14

RAM cell
15

Read/Write
logic

Read/Write
logic

Read/Write
logic

Read/Write
logic

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data input
Read/Write
X

Column select
0

Column 2-to-4 Decoder

decoder with enable
21
20
A1

A0

Data
output

Enable

Chip select

Chapter 8 17

RAM ICs with > 1 Bit/Word

Word length can be quite high.
To better balance the number of words
and word length, use ICs with > 1
bit/word
Example

2 Data input bits

2 Data output bits
Row select selects 4 rows
Column select selects 2 pairs of columns
Chapter 8 18

Block Diagram of an 82 RAM

A2

Row decoder
2-to-4
Decoder 0
21

A1

20

RAM cell
0

RAM cell
1

RAM cell
2

RAM cell
3

Row RAM cell

4
select

RAM cell
5

RAM cell
6

RAM cell
7

RAM cell
8

RAM cell
9

RAM cell
10

RAM cell
11

RAM cell
12

RAM cell
13

RAM cell
14

RAM cell
15

Read/Write
logic

Read/Write
logic

Read/Write
logic

Read/Write
logic

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data in
Data out
Read/ Bit
Write select

Data input 0
Data input 1
Read/Write

Column select
0
1
1-to-2
Decoder
Column
decoder with enable
Enable
20
A0

Data
Output 0

Chip select

Data
Output 1

Chapter 8 19

Making Larger Memories

Using the CS lines, we
can make larger
memories from smaller
ones by tying all
address, data, and R/W
lines in parallel, and
using the decoded
higher order address
bits to control CS.
Using the 4-Word by 1Bit memory from
before, we construct a A3
A2
16-Word by
A1
1-Bit memory.

A0
R/W

Decoder

Data In

D3

A1 D-In
A0
R/W
CS D-Out

D2

A1 D-In
A0
R/W
CS D-Out

D1

A1 D-In
A0
R/W
CS D-Out

S1 D0
S0

A1 D-In
A0
R/W
CS D-Out

Data Out

Chapter 8 20

Making Wider Memories

To construct wider
memories from narrow
ones, we tie the address
and control lines in
parallel and keep the data
lines separate.
For example, to make a 4word by 4-bit memory
from 4, 4-word by 1-bit
memories

Note: Both 16x1 and 4x4 A1

memories take 4-chips A0
and hold 16 bits of data. R/W

Data In

3210

A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out
A1 D-In
A0
R/W
CS D-Out

CS

Data Out

3210

Chapter 8 21

Block Diagram of a 256K8 RAM

Address
Lines
17 16
Memory Enable

Read/ Write

2-to-4 Decoder
EN
3 2 1 0

Lines 0 -15
16

Input
Data
8

0 - 65535

64K 8 RAM
DATA
ADRS

CS
R/W
65536- 131071

64K 8 RAM
DATA
ADRS

CS
R/W
131072 - 196607

64K 8 RAM
DATA
ADRS

CS
R/W
196608 - 262143

64K 8 RAM
DATA
ADRS
CS
R/W

8
Output Data

Chapter 8 22

Block Diagram of a 64K16 RAM

16 Input Data Lines
8
Address

16
64K 8 RAM
8
16

Chip Select
Read / Write

64K 8 RAM
8

DATA
ADRS

16

CS
R/W

DATA
ADRS

CS
R/W

16 Output Data Lines

Chapter 8 23

Block Diagram of a 256K16 RAM

Address
Lines
17 16
Memory Enable

Read/ Write

2-to-4 Decoder
EN
3 2 1 0

16 Input Data Lines

8
8
Lines 0 -15
16

64K 8 RAM

64K 8 RAM

DATA
ADRS
CS
R/W

DATA

ADRS
CS
R/W

64K 8 RAM

64K 8 RAM

DATA

DATA

ADRS

CS
R/W

64K 8 RAM

64K 8 RAM

DATA

DATA

ADRS

CS
R/W

CS
R/W
64K 8 RAM

64K 8 RAM

DATA

DATA
ADRS
CS
R/W

ADRS

CS
R/W

ADRS

ADRS
CS
R/W
8

16 Output Data Lines

Chapter 8 24

Dynamic RAM (DRAM)

Basic Principle: Storage of information
on capacitors.
Charge and discharge of capacitor to
change stored value
Use of transistor as switch to:
Store charge
Charge or discharge

See next slide for circuit, hydraulic

analogy, and logical model.
Chapter 8 25

Dynamic RAM (continued)

Select
T

C
DRAM cell
(b)

(a)

(c)

Write 1

Select

Stored 0

Stored 1

To Pump

(d)

Write 0
(e)

Read 1

Read 0

DRAM cell
model
(h)

(f)

(g)

Chapter 8 26

Dynamic RAM - Bit Slice

C is driven by 3-state
drivers
Sense amplifier is used
to change the small
voltage change on C
into H or L
In the electronics, B, C,
and the sense amplifier
output are connected to
make destructive read
into non-destructive
read

Word
select
0

Select

Word
select
0

DRA M cell
model

DRA M cell
Word
select
1
DRA M cell

Select
2- 1
D

2
- 1

DRA M cell
model

DRA M cell
Read/Write
logic
Sense
amplifier

Data in

Data in
Data out
Read/ Bit
Write
select
(b) Symbol

Write logic
Read/
Write

Bit
select

Read logic

Data out

(a) L ogic diagram

Chapter 8 27

Dynamic RAM - Block Diagram

Refresh
Controller

Row
Address

Row Address
Register

RAS

Row Timing
Logic

CAS

Refresh
Counter

Row Address
Register

DRAM
Bit Slice

DRAM
Bit Slice

DRAM
Bit Slice

Input / Output Logic

R/W
OE
Column
Address

Row Timing
Logic

Column Decoder
Data In /
Data Out

Chapter 8 28

Dynamic RAM - Block Diagram

Refresh Controller and Refresh Counter
Read and Write Operations
Application of row address
The row address is used to select the row of cells to be read within the memory.

Application of column address

The column address is used to select the word to be placed on the output from the data read
from the row of cells.

Why is the address split?

The address is split to roughly halve the large number of address pins on the typical RAM IC.

Why is the row address applied first?

Since the data must be read from the cells before it can be selected, the row address must be
applied first.

Chapter 8 29

Dynamic RAM Read Timing

20 ns
Clock

Address

T1

T2

T3

T4

T1

Column
Address

Row
Address

RAS

CAS
Output
enable
Read/
Write
Data
output

Hi-Z

Data valid
65 ns
Read Cycle

Chapter 8 30

Dynamic RAM Write Timing

20 ns
Clock

Address

T1
Row
Address

T2

T3

T4

T1

Column
Address

RAS

CAS
Output
enable
Read/
Write
Data
output

Data valid
75 ns
Write Cycle

Chapter 8 31

DRAM Types
DRAM Types:
Synchronous DRAM (SDRAM)
Double Data Rate SDRAM (DDR SDRAM)
RAMBUS DRAM (RDRAM)

Justification for effectiveness of these types

DRAM often used as a part of a memory hierarchy (See details in
chapter 14)
Reads from DRAM bring data into lower levels of the hierarchy
Transfers from DRAM involve multiple consecutively addressed
words
Many words are internally read within the DRAM ICs using a
single row address and captured within the memory
This read involves a fairly long delay
Chapter 8 32

DRAM Types
Justification for effectiveness of these types (continued)
These words are then transferred out over the memory data
bus using a series of clocked transfers
These transfers have a low delay, so several can be done in a
short time
The column address is captured and used by a synchronous
counter within the DRAM to provide consecutive column
addresses for the transfers

Burst read the resulting multiple word read from

consecutive addresses

Chapter 8 33

Synchronous DRAM
Transfers to and from the DRAM are synchronize with a clock
Synchronous registers appear on:
Address input
Data input
Data output

Column address counter

for addressing internal data to be transferred on each clock cycle
beginning with the column address counts up to column address + burst
size 1

Example: Memory data path width: 1 word = 4 bytes

Burst size: 8 words = 32 bytes
Memory clock frequency: 5 ns
Latency time (from application of row address until first word
available): 4 clock cycles
Read cycle time: (4 + 8) x 5 ns = 60 ns
Memory Bandwidth: 32/(60 x 10 -9) = 533 Mbytes/sec
Chapter 8 34

Double Data Rate Synchronous DRAM

Transfers data on both edges of the clock
Provides a transfer rate of 2 data words per
clock cycle
Example: Same as for synchronous DRAM
Read cycle time = 60 ns
Memory Bandwidth: (2 x 32)/(60 x 10-9) = 1.066
Mbytes/sec

Chapter 8 35

RAMBUS DRAM (RDRAM)

Uses a packet-based bus for interaction between the RDRAM ICs and the
memory bus to the processor
The bus consists of:
A 3-bit row address bus
A 5-bit column address bus
A 16 or 18-bit (for error correction) data bus

The bus is synchronous and transfers on both edges of the clock

Packets are 4-clock cycles long giving 8 transfers per packet representing:
A 12-bit row address packet
A 20-bit column address packet
A 128 or 144-bit data packet

Multiple memory banks are used to permit concurrent memory accesses

with different row addresses
The electronic design is sophisticated permitting very fast clock speeds
Chapter 8 36

Arrays of DRAM Integrated Circuits

Similar to arrays of SRAM ICs, but there are
differences typically handled by an IC called a
DRAM controller:
Separation of the address into row address and
column address and timing their application
Providing RAS and CAS and timing their
application
Performing refresh operations at required intervals
Providing status signals to the rest of the system
(e.g., indicating whether or not the memory is active
or is busy performing refresh)
Chapter 8 37

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Chapter 8 38