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Sequential logic

Sequential circuits

Timing methodologies

metastability and synchronization

Basic registers

cascading flip-flops for proper operation


clock skew

Asynchronous inputs

simple circuits with feedback


latches
edge-triggered flip-flops

shift registers
simple counters

Hardware description languages and sequential logic

VI - Sequential

Copyright 2004, Gaetano B

Sequential circuits

Circuits with feedback

outputs = f(inputs, past inputs, past outputs)


basis for building "memory" into logic circuits
door combination lock is an example of a sequential circuit

state is memory
state is an "output" and an "input" to combinational logic
combination storage elements are also memory
new

equal

reset

value
C1

C2

C3

multiplexer

mux
control

comb. logic
state

comparator
equal

VI - Sequential

clock

open/closed

Copyright 2004, Gaetano B

Circuits with feedback

How to control feedback?

what stops values from cycling around endlessly

X1
X2

Xn

VI - Sequential

switching
network

Z1
Z2

Zn

Copyright 2004, Gaetano B

Simplest circuits with feedback

Two inverters form a static memory cell

will hold value as long as it has power applied


"1"
"stored value"
"0"

How to get a new value into the memory cell?

selectively break feedback path


load new value into cell
"remember"
"data"

VI - Sequential

"load"

Copyright 2004, Gaetano B

"stored value"

Memory with cross-coupled gates

Cross-coupled NOR gates

similar to inverter pair, with capability to force output to 0 (reset=1) or 1


(set=1)
Q

Q'

R
S

Cross-coupled NAND gates

similar to inverter pair, with capability to force output to 0 (reset=0) or 1


(set=0)

S'
R'

VI - Sequential

S'

R'

Copyright 2004, Gaetano B

Q'

Timing behavior

Reset

Hold

Q'

Set

Reset

Set

100

Race

R
S
Q
\Q

VI - Sequential

Copyright 2004, Gaetano B

State behavior or R-S latch

Q'

Truth table of R-S latch behavior


Q Q'
0 1
S
0
0
1
1

R
0
1
0
1

Q
hold
0
1
unstable

Q Q'
1 0

Q Q'
0 0

Q Q'
1 1

VI - Sequential

Copyright 2004, Gaetano B

Theoretical R-S latch behavior

Q'

SR=10
SR=00
SR=01

SR=01

Q Q'
0 1

SR=01

Q Q'
1 0

SR=00
SR=10

SR=10

SR=11

State diagram

states: possible values


transitions: changes
based on inputs

SR=11

SR=01
possible oscillation
between states 00 and 11

VI - Sequential

Q Q'
0 0

SR=11
SR=00
SR=11

SR=00

SR=10
Q Q'
1 1

Copyright 2004, Gaetano B

Observed R-S latch behavior

Q'

Very difficult to observe R-S latch in the 1-1 state

one of R or S usually changes first

Ambiguously returns to state 0-1 or 1-0

a so-called "race condition"


or non-deterministic transition

SR=10

SR=00
SR=01

SR=01

Q Q'
0 1

SR=01

Q Q'
1 0

SR=00
SR=10

SR=10

SR=11

SR=11
SR=00

VI - Sequential

Q Q'
0 0

SR=11
SR=00

Copyright 2004, Gaetano B

R-S latch analysis


Break feedback path

Q'

S
S
0
0
0
0
1
1
1
1

R
0
0
1
1
0
0
1
1

Q(t)

Q(t)
0
1
0
1
0
1
0
1

VI - Sequential

Q(t+)
0
hold
1
0
reset
0
1
set
1
X not allowed
X

Q(t+)

S
R

Q(t)

R
characteristic equation
Q(t+) = S + R Q(t)

Copyright 2004, Gaetano B

10

Activity: R-S latch using NAND gates


R

Q'

R
0
0
1
1
0
0
1
1

R
S

S
0
0
0
0
1
1
1
1

Q(t)

S
1
1
1
1
0
0
0
0

R
1
1
0
0
1
1
0
0

VI - Sequential

Q(t)
0
1
0
1
0
1
0
1

Q(t+)
0
1
0
0
1
1
X
X

hold
reset

Q(t)

set
not allowed

R
characteristic equation
Q(t+) = S + R Q(t)

Copyright 2004, Gaetano B

11

Gated R-S latch

Control when R and


S inputs matter

otherwise, the
slightest glitch on
R or S while
enable is low could
cause
change in value
stored

R'

enable'
Q'

S'

Set

100

Reset

S'
R'
enable'
Q
Q'

VI - Sequential

Copyright 2004, Gaetano B

12

Clocks

Used to keep time

wait long enough for inputs (R' and S') to settle


then allow to have effect on value stored

Clocks are regular periodic signals

period (time between ticks)


duty-cycle (time clock is high between ticks - expressed as % of
period)
duty cycle (in this case, 50%)

period

VI - Sequential

Copyright 2004, Gaetano B

13

Clocks (contd)

Controlling an R-S latch with a clock

can't let R and S change while clock is active (allowing R and S to


pass)
only have half of clock period for signal changes to propagate
signals must be stable for the other half of clock period
R

clock
S

Q
S
stablechanging stable changing stable
R and S
clock

VI - Sequential

Copyright 2004, Gaetano B

14

Cascading latches

Connect output of one latch to input of another


How to stop changes from racing through chain?

need to be able to control flow of data from one latch to the next
move one latch per clock period
have to worry about logic between latches (arrows) that is too fast

clock

VI - Sequential

Copyright 2004, Gaetano B

15

Master-slave structure

Break flow by alternating clocks (like an air-lock)

use positive clock to latch inputs into one R-S latch


use negative clock to change outputs with another R-S latch

View pair as one basic unit

master-slave flip-flop
twice as much logic
output changes a few gate delays after the falling edge of clock
but does not affect any cascaded flip-flops
slave stage

master stage

CLK

VI - Sequential

Copyright 2004, Gaetano B

16

The 1s catching problem

In first R-S stage of master-slave FF

0-1-0 glitch on R or S while clock is high is "caught" by master stage


leads to constraints on logic to be hazard-free
slave stage

master stage

Set
S
R
CLK
P
P
Q
Q

1s
Reset catch

VI - Sequential

P
P

CLK

Master
Outputs
Slave
Outputs

Copyright 2004, Gaetano B

17

D flip-flop
Make S and R complements of each other

eliminates 1s catching problem


can't just hold previous value
(must have new value ready every clock period)
value of D just before clock goes low is what is stored in flip-flop
can make R-S flip-flop by adding logic to make D = S + R Q
slave stage

master stage

CLK

VI - Sequential

Copyright 2004, Gaetano B

10 gates

18

Edge-triggered flip-flops

More efficient solution: only 6 gates

sensitive to inputs only near edge of clock signal (not while high)

holds D when
clock goes low

0
R

Clk=1
Q

negative edge-triggered D
flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time
constraints to successfully
capture input

0
holds D when
clock goes low
D

VI - Sequential

characteristic equation
Q(t+1) = D

Copyright 2004, Gaetano B

19

Edge-triggered flip-flops (contd)

Step-by-step analysis
D

Clk=0

Clk=0
S

S
D

new D
new D old D

when clock goes high-to-low


data is latched
VI - Sequential
Copyright

2004,

when clock is low


Gaetano Bdata is held

20

Edge-triggered flip-flops (contd)

Positive edge-triggered

inputs sampled on rising edge; outputs change after rising edge

Negative edge-triggered flip-flops

inputs sampled on falling edge; outputs change after falling edge


100

D
CLK
Qpos
Qpos
Qneg
Qneg

VI - Sequential

positive edge-triggered FF
negative edge-triggered FF

Copyright 2004, Gaetano B

21

Timing methodologies

Rules for interconnecting components and clocks

guarantee proper operation of system when strictly followed

Approach depends on building blocks used for memory


elements

we'll focus on systems with edge-triggered flip-flops

found in programmable logic devices

many custom integrated circuits focus on level-sensitive latches

Basic rules for correct timing:

(1) correct inputs, with respect to time, are provided to the flipflops
(2) no flip-flop changes state more than once per clocking event

VI - Sequential

Copyright 2004, Gaetano B

22

Timing methodologies (contd)

Definition of terms

clock:

periodic event, causes state of memory element to change


can be rising edge or falling edge or high level or low level
setup time: minimum time before the clocking event by which the
input must be stable (Tsu)
hold time: minimum time after the clocking event until which the
input must remain stable (Th)
data

Tsu Th

D Q

D Q

input
clock

clock

there is a timing "window"


around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized

VI - Sequential

stable changing
data
clock

Copyright 2004, Gaetano B

23

Comparison of latches and flip-flops

D Q
CLK
positive
edge-triggered
flip-flop

D
CLK
Qedge

D Q
G

Qlatch

CLK
transparent
(level-sensitive)
latch

VI - Sequential

behavior is the same unless input changes


while the clock is high

Copyright 2004, Gaetano B

24

Comparison of latches and flip-flops


(contd)
Type

When inputs are sampled

unclocked
latch

always

When output is valid

propagation delay from input change

level-sensitive clock high


latch
(Tsu/Th around falling
edge of clock)

propagation delay from input change


or clock edge (whichever is later)

master-slave
flip-flop

propagation delay from falling edge


of clock

clock high
(Tsu/Th around falling
edge of clock)

negative
clock hi-to-lo transition propagation delay from falling edge
edge-triggered (Tsu/Th around falling of clock
flip-flop
edge of clock)

VI - Sequential

Copyright 2004, Gaetano B

25

Typical timing specifications

Positive edge-triggered D flip-flop

setup and hold times


minimum clock width
propagation delays (low to high, high to low, max and typical)

Clk

Tsu

Th

1.8
ns

0.5
ns
Tw
3.3
ns

Tpd
3.6 ns
1.1 ns

Tsu

Th

1.8
ns

0.5
ns
Tw
3.3
ns
Tpd
3.6 ns
1.1 ns

all measurements are made from the clocking event (the rising edge of the clock)

VI - Sequential

Copyright 2004, Gaetano B

26

Cascading edge-triggered flip-flops

Shift register

IN

new value goes into first stage


while previous value of first stage goes into second stage
consider setup/hold/propagation delays (prop must be > hold)
D Q

Q0

D Q

Q1

OUT

CLK

100
IN
Q0
Q1
CLK

VI - Sequential

Copyright 2004, Gaetano B

27

Cascading edge-triggered flip-flops


(contd)

Why this works

propagation delays exceed hold times


clock width constraint exceeds setup time
this guarantees following stage will latch current value before it
changes to new value
In

Tsu
1.8ns

Q0

Tsu
1.8ns
Tp
1.1-3.6ns

Tp
1.1-3.6ns

timing constraints
guarantee proper
operation of
cascaded components

Q1
assumes infinitely fast
distribution of the clock

CLK
Th
0.5ns

VI - Sequential

Th
0.5ns

Copyright 2004, Gaetano B

28

Clock skew

The problem

correct behavior assumes next state of all storage elements


determined by all storage elements at the same time
this is difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
effect of skew on cascaded flip-flops:
100

In
Q0
Q1
CLK0
CLK1

CLK1 is a delayed
version of CLK0

original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

VI - Sequential

Copyright 2004, Gaetano B

29

Summary of latches and flip-flops

Development of D-FF

level-sensitive used in custom integrated circuits

edge-triggered used in programmable logic devices


good choice for data storage register

Historically J-K FF was popular but now never used

can be made with 4 switches

similar to R-S but with 1-1 being used to toggle output (complement state)
good in days of TTL/SSI (more complex input function: D = J Q + K Q
not a good choice for PALs/PLAs as it requires 2 inputs
can always be implemented using D-FF

Preset and clear inputs are highly desirable on flip-flops

used at start-up or to reset system to a known state

VI - Sequential

Copyright 2004, Gaetano B

30

Metastability and asynchronous


inputs

Clocked synchronous circuits

Asynchronous circuits

inputs, state, and outputs sampled or changed in relation to a


common reference signal (called the clock)
e.g., master/slave, edge-triggered
inputs, state, and outputs sampled or changed independently of a
common reference signal (glitches/hazards a major concern)
e.g., R-S latch

Asynchronous inputs to synchronous circuits

inputs can change at any time, will not meet setup/hold times
dangerous, synchronous inputs are greatly preferred
cannot be avoided (e.g., reset signal, memory wait, user input)

VI - Sequential

Copyright 2004, Gaetano B

31

Synchronization failure

Occurs when FF input changes close to clock edge

the FF may enter a metastable state neither a logic 0 nor 1


it may stay in this state an indefinite amount of time
this is not likely in practice but has some probability
logic 1

logic 0

logic 1

small, but non-zero probability


that the FF output will get stuck
an in-between
state
VI - in
Sequential
Copyright

logic 0
oscilloscope traces demonstrating
synchronizer failure and eventual
decayB
to steady state
32
2004, Gaetano

Dealing with synchronization failure

Probability of failure can never be reduced to 0, but it can be reduced

(1) slow down the system clock


this gives the synchronizer more time to decay into a steady state;
synchronizer failure becomes a big problem for very high speed systems
(2) use fastest possible logic technology in the synchronizer
this makes for a very sharp "peak" upon which to balance
(3) cascade two synchronizers
this effectively synchronizes twice (both would have to fail)

asynchronous
input

synchronized
input

Q
Clk

synchronous system

VI - Sequential

Copyright 2004, Gaetano B

33

Handling asynchronous inputs

Never allow asynchronous inputs to fan-out to more than one flip-flop

synchronize as soon as possible and then treat as synchronous signal

Clocked
Synchronous
System
Async
Input

D Q

Synchronizer
Q0

Async
Input D Q

D Q

Clock

Clock
D Q

Q1

Clock

VI - Sequential

Copyright 2004, Gaetano B

Q0

D Q

Q1

Clock

34

Handling asynchronous inputs


(contd)

What can go wrong?

input changes too close to clock edge (violating setup time


constraint)

In
Q0
Q1

In is asynchronous and
fans out to D0 and D1
one FF catches the
signal, one does not
inconsistent state may
be reached!

CLK

VI - Sequential

Copyright 2004, Gaetano B

35

Flip-flop features

Reset (set state to 0) R

Preset or set (set state to 1) S (or sometimes P)

Dnew = R' Dold + S


Dnew = R' Dold + R'S

(set-dominant)
(reset-dominant)

Selective input capability (input enable or load) LD or EN

synchronous: Dnew = Dold + S (when next clock edge arrives)


asynchronous: doesn't wait for clock, quick but dangerous

Both reset and preset

synchronous: Dnew = R' Dold (when next clock edge arrives)


asynchronous: doesn't wait for clock, quick but dangerous

multiplexor at input: Dnew = LD' Q + LD Dold


load may or may not override reset/set (usually R/S have priority)

Complementary outputs Q and Q'

VI - Sequential

Copyright 2004, Gaetano B

36

Registers

Collections of flip-flops with similar controls and logic

stored values somehow related (for example, form binary value)


share clock, reset, and set lines
similar logic at each stage

Examples

shift registers
counters

OUT1

OUT2

OUT3

OUT4

"0"
R S
D Q

R S
D Q

R S
D Q

R S
D Q

CLK
IN1

VI - Sequential

IN2

IN3

Copyright 2004, Gaetano B

IN4

37

Shift register

Holds samples of input

store last 4 input values in sequence


4-bit shift register:
OUT1
IN

D Q

D Q

OUT2

OUT3

D Q

OUT4

D Q

CLK

VI - Sequential

Copyright 2004, Gaetano B

38

Universal shift register

Holds 4 values

serial or parallel inputs


serial or parallel outputs
permits shift left or right
shift in new values from left or right
output

left_in
left_out
clear
s0
s1

right_out
right_in
clock

input

VI - Sequential

clear sets the register contents


and output to 0
s1 and s0 determine the shift function
s0
0
0
1
1

s1
0
1
0
1

Copyright 2004, Gaetano B

function
hold state
shift right
shift left
load new input

39

Design of universal shift register

Consider one of the four flip-flops

new value at next clock cycle:

clears0
1

0
0
0
0
0
1
0
1

s1

0
1
0
1

new value
0
output
output value of FF to left (shift righ
output value of FF to right (shift le
input

Nth cell
to N-1th
cell

to N+1th
cell

Q
D

CLK

CLEAR
0 1 2 3 s0 and s1
control mux

VI - Sequential

Q[N-1]
(left)

Copyright 2004, Gaetano B

Input[N]

Q[N+1]
(right)

40

Shift register application

Parallel-to-serial conversion for serial transmission


parallel outputs

parallel inputs

serial transmission

VI - Sequential

Copyright 2004, Gaetano B

41

Pattern recognizer

Combinational function of input samples

in this case, recognizing the pattern 1001 on the single input


signal
OUT

OUT1
IN

D Q

D Q

OUT2
D Q

OUT3

OUT4

D Q

CLK

VI - Sequential

Copyright 2004, Gaetano B

42

Counters

Sequences through a fixed set of patterns

in this case, 1000, 0100, 0010, 0001


if one of the patterns is its initial state (by loading or set/reset)
OUT1
IN

D Q

D Q

OUT2

OUT3

D Q

OUT4

D Q

CLK

VI - Sequential

Copyright 2004, Gaetano B

43

Activity

How does this counter work?


OUT1
IN

D Q

OUT2

D Q

OUT3

D Q

OUT4

D Q

CLK

Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011,
0001, 0000
Known as Mobius (or Johnson) counter

VI - Sequential

Copyright 2004, Gaetano B

44

Binary counter

Logic between registers (not just multiplexer)

XOR decides when bit should be toggled


always for low-order bit,
only when first bit is true for second bit,
and so on
OUT1
D Q

OUT2
D Q

OUT3
D Q

OUT4
D Q

CLK

"1"

VI - Sequential

Copyright 2004, Gaetano B

45

Four-bit binary synchronous upcounter

Standard component with many applications

positive edge-triggered FFs w/ synchronous load and clear inputs


parallel load data from D, C, B, A
enable inputs: must be asserted to enable counting
EN
RCO: ripple-carry out used for cascading counters

high when counter is in its highest state 1111


implemented using an AND gate
(2) RCO goes high

D
C
RCO
B
QD
A
QC
LOAD QB
QA
CLK
CLR

(3) High order 4-bits


are incremented
(1) Low order 4-bits = 1111

VI - Sequential

Copyright 2004, Gaetano B

46

Offset counters

Starting offset counters use of synchronous load

"1"

e.g., 0110, 0111, 1000, 1001,


1010, 1011, 1100, 1101, 1111, 0110, . . .

"0"
"1"
"1"
"0"

"0"

RCO
QD
D
QC
C
QB
B
QA
A
LOAD
CLK
CLR

Ending offset counter comparator for ending value

e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

"1"
"0"
"0"
"0"
"0"

EN

Combinations of the above (start and stop value)

VI - Sequential

Copyright 2004, Gaetano B

EN
D
C
B
A
LOAD
CLK
CLR

RCO
QD
QC
QB
QA

47

Hardware Description Languages


and Sequential Logic

Flip-flops

representation of clocks - timing of state changes


asynchronous vs. synchronous

Shift registers
Simple counters

VI - Sequential

Copyright 2004, Gaetano B

48

Flip-flop in Verilog

Use always block's sensitivity list to wait for clock edge

module dff (clk, d, q);


input clk, d;
output q;
reg
q;
always @(posedge clk)
q = d;
endmodule

VI - Sequential

Copyright 2004, Gaetano B

49

More Flip-flops

Synchronous/asynchronous reset/set

single thread that waits for the clock


three parallel threads only one of which waits for the clock
Synchronous

module dff
input
output
reg

(clk, s, r, d, q);
clk, s, r, d;
q;
q;

always @(posedge clk)


if (r)
q = 1'b0;
else if (s) q = 1'b1;
else
q = d;
endmodule

Asynchronous
module dff
input
output
reg

(clk, s, r, d, q);
clk, s, r, d;
q;
q;

always @(posedge r)
q = 1'b0;
always @(posedge s)
q = 1'b1;
always @(posedge clk)
q = d;
endmodule

VI - Sequential

Copyright 2004, Gaetano B

50

Incorrect Flip-flop in Verilog

Use always block's sensitivity list to wait for clock to change

module dff (clk, d, q);


input clk, d;
output q;
reg
q;
always @(clk)
q = d;

Not correct! Q will


change whenever the
clock changes, not
just on an edge.

endmodule

VI - Sequential

Copyright 2004, Gaetano B

51

Blocking and Non-Blocking


Assignments

Blocking assignments (X=A)

Non-blocking assignments (X<=A)

completes the assignment before continuing on to next statement


completes in zero time and doesnt change the value of the target
until a blocking point (delay/wait) is encountered

Example: swap

always @(posedge CLK)


begin
temp = B;
B = A;
A = temp;
end

VI - Sequential

always @(posedge CLK)


begin
A <= B;
B <= A;
end

Copyright 2004, Gaetano B

52

Register-transfer-level (RTL)
Assignment

Non-blocking assignment is also known as an RTL assignment

if used in an always block triggered by a clock edge


all flip-flops change together

// B,C,D all get the value of A


always @(posedge clk)
begin
B = A;
C = B;
D = C;
end

VI - Sequential

// implements a shift register too


always @(posedge clk)
begin
B <= A;
C <= B;
D <= C;
end

Copyright 2004, Gaetano B

53

Mobius Counter in Verilog


initial
begin
A =
B =
C =
D =
end

1b0;
1b0;
1b0;
1b0;

always @(posedge clk)


begin
A <= ~D;
B <= A;
C <= B;
D <= C;
end

VI - Sequential

Copyright 2004, Gaetano B

54

Binary Counter in Verilog


module binary_counter (clk, c8, c4, c2, c1);
input clk;
output c8, c4, c2, c1;

module binary_counter (clk, c8, c4, c2, c1, rco);

reg [3:0] count;

input clk;
output c8, c4, c2, c1, rco;

initial begin
count = 0;
end

reg [3:0] count;


reg rco;

always @(posedge clk) begin


count = count + 4b0001;
end

initial begin . . . end

assign
assign
assign
assign

assign
assign
assign
assign
assign

c8
c4
c2
c1

=
=
=
=

count[3];
count[2];
count[1];
count[0];

always @(posedge clk) begin . . . end


c8 = count[3];
c4 = count[2];
c2 = count[1];
c1 = count[0];
rco = (count == 4b1111);

endmodule

endmodule

VI - Sequential

Copyright 2004, Gaetano B

55

Sequential logic summary

Fundamental building block of circuits with state

Timing methodologies

synchronizer failure: what it is and how to minimize its impact

Basic registers

use of clocks
cascaded FFs work because propagation delays exceed hold times
beware of clock skew

Asynchronous inputs and their dangers

latch and flip-flop


R-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop

shift registers
counters

Hardware description languages and sequential logic

VI - Sequential

Copyright 2004, Gaetano B

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