Constellations 2010 Silicon Valley - Complete Slide Set

Constellations Conference
Silicon Valley 2010
© IPextreme, Inc.
Confidential Information.
A collaborative group of IP
companies working together to
serve common customers
MCU & Periph- Audio Video Inter- Network- On-Chip Memory Encrypt-
DSP erals faces ing Interconnect ion
ESD
Compilers
with
Data Flow
Services
Legend Soft IP Hard IP Software Other

Agenda
8:30am Breakfast
9:15am Welcome & Introductions Warren Savage
9:25am Keynote Presentation Jim Hogan
9:40am Increasing ESD Challenges Stephen Fairbanks
10:00am Integrating high performance, ultra-low power Serge Maginot

Clockless IP
10:20am Turn your Engineering Cost Center to a Profit Center Rick Tomihiro
10:40am Panel: IP Business Models
11:40am Lunch
© IPextreme, Inc. Confidential Information. Slide 3

Agenda
12:15pm Leveraging Your On-chip Networks and Maximizing Jack Browne

Multi-layer Bus Designs
12:35pm The Need for a New Breed of Embedded NVM Jim Lipman
12:55pm Can You Trust Your IP Vendor? How Not to Lose Hal Barbour
Sleep Over it
1:15pm Bringing HD video to multimedia applications Philip Han
1:35pm Afternoon Break & Refreshments
1:55pm Ultra Low Power CoolFlux DSP Cores Sweetening Sven De Bie
Your Green Chip Dreams
2:15pm Rest in the comfort and security of knowing you have Farzad Zarrinfar
Selected the Optimum Memory IPs
2:35pm The role of Networking IP in Wired/Wireless Surya Hotha

Applications

Agenda
2:55pm Panel: Technical Considerations
3:55pm Luck Draw – Apple iPad
4:10pm Closing Statement Warren Savage
4:20pm Networking
5:00pm End

IPextreme Constellations Conference - Silicon Valley 2010
Jim Hogan - Wednesday, March 31, 2010
Major Market Directions
• Exploding HW complexity
– $$$ per chip only allow major volume components to be successful
• Exploding SW complexity
– Growth 10 fold in 10 years
• Costs driving out smaller semi’s
– Big semi’s aggregating, collaborating, shrinking, disappearing
• Major players (Japan Inc) looking for future direction
– Foundry agnostic
– Content, system expertise still strongholds
• New players (China Inc) driving into every aspect of Semi’s
– Video, local consumption, local standards driving models
– Closing on innovation gap quickly
HW Development
• Industry investment is 25.0
stagnant 20.0
• Costs are escalating 15.0
beyond the reach of many 10.0
% Yearly Growth
fabless semi’s 5.0
0.0
• Substantial investment dip
-5.0
in recent past has rippled
to EDA/IP -10.0
-15.0
– Outlook for the next 5 years
is slightly better than single HW Growth Rate (%)
-20.0
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
0.4 -8.3 0.4 20.5 7.9 10.4 7.3 -5.3 -17.8 5.5 12.0 14.1 14.1 9.5 6.4
digit growth HW Growth Rate (%)
Source:
Source: GLOBAL
GLOBAL SYSTEM
SYSTEM IC
IC (ASSP/ASIC)
(ASSP/ASIC) SERVICE
SERVICE MANAGEMENT
MANAGEMENT
REPORT
REPORT -- 8/09
8/09
Industry Trends –SW IP Outpaces HW IP
2007 2008 2009 2010 2011 2012 2013 2014 2015
Hardware product 18,830 17,837 14,665 15,478 17,336 19,786 22,574 24,713 26,283
development ($M)
HW IP ($M) 3,088 3,104 2,713 3,049 3,641 4,432 5,395 6,302 7,175
• Percent HW prod dev 16.4 17.4 18.5 19.7 21 22.4 23.9 25.5 27.3
(%)
• Growth rate (%) 13.6 0.5 -12.6 12.4 19.4 21.7 21.7 16.8 13.9
HW Growth Rate (%) 7.3 -5.3 -17.8 5.5 12.0 14.1 14.1 9.5 6.4
HW Growth Baseline YR 42.6 35.1 11.0 17.2 31.3 49.8 70.9 87.1 99.0
‘2000
SW product 6,384 7,003 6,291 7,365 9,450 11,867 14,825 18,587 22,921
development ($M)
SW IP ($M) 441 616 692 987 1,503 2,207 3,202 4,628 6,555
• Percent SW prod dev 6.9 8.8 11 13.4 15.9 18.6 21.6 24.9 28.6
(%)
• SW Growth (%) 61.5 39.9 12.3 42.6 52.3 46.9 45.1 44.5 41.6
SW Growth Rate (%) 19.39 9.70 -10.17 17.07 28.31 25.58 24.93 25.38 23.32
SW Growth Baseline YR 182.7 210.1 178.6 226.2 318.5 425.6 556.6 723.2 915.1
‘2000
TOTAL product 25,214 24,840 20,956 22,843 26,787 31,653 37,399 43,300 49,204
development ($M)
Source:
Source: GLOBAL
GLOBAL SYSTEM
SYSTEM IC
IC (ASSP/ASIC)
(ASSP/ASIC) SERVICE
SERVICE MANAGEMENT
MANAGEMENT REPORT
REPORT -- 8/09
8/09
SW Growth as part of the Semiconductor
Industry Outpaces HW significantly
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
-100.0
2001 2002
2003 2004
2005 2006
2007 2008 SW Growth (%)
2009 2010 HW Growth (%)
2011 2012
2013 2014 2015
HW Growth (%) SW Growth (%)
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
HW Growth (%) 0.4 -7.9 -7.5 11.4 20.3 32.8 42.6 35.1 11.0 17.2 31.3 49.8 70.9 87.1 99.0
SW Growth (%) 6.1 4.2 17.9 60.9 95.0 136.8 182.7 210.1 178.6 226.2 318.5 425.6 556.6 723.2 915.1
Source:
Source: GLOBAL
GLOBAL SYSTEM
SYSTEM ICIC (ASSP/ASIC)
(ASSP/ASIC) SERVICE
SERVICE
MANAGEMENT
MANAGEMENT REPORT
REPORT -- 8/09
8/09
SoC New World
• Fabless and IDMs will:
– Utilize SoCs to integrate system application knowledge and
capture user experience Multi-Processor SoC
• Capture more value than standard discrete component
– Deploy heterogeneous multiple processors running distinct
hardware operating software Custom
CPU DSP
DSP
– Focus increasingly limited resources on architecture and
partnerships in
software, with ecosystem
non- differentiated IP, physical
implementation, foundry and test
• Core competencies in specialized
I/O I/O I/O
differentiating IP (hardware and FPGA
software) and in SoC integration strength FPGA
Periph
eMEM
MEM
• Shed the need for ongoing investment in ubiquitous design

and commoditized assets such as standardized intellectual
property (USB, PCI, DDR…)
SoC Platform Standard
• Requirements
– Heterogeneous integration of any IP core on any SoC at any
time… to optimize for the system software application
– Flexibility to match system application needs without over-design
– Predictable logical and physical implementation…and silicon proven
– Rapid adaptation to changing markets
– Automated derivative design and verification
• Elements
– Complete SoC communication architectures
• System level services – quality of service ( QoS), security, power, error management
• Flexible sockets
• Scalable fabrics
– Cycle accurate architectural performance models (i.e. Carbon)
– Coherent SoC capture, refinement, and verification environment
Android Based System
PVR HD Streaming Android Android Android
TV App
App Player App App App App App
Android
Core
Application Framework
Adobe® Libraries
Flash
Android Libraries Webkit For BD-J
Digital
3rd Party Dalvik VM
Home
Middleware
Video/Graphics
DirectFB
Libraries
Digital Rights Mgmt

Conditional Access Demur
µCode
Audio
µCode
Video
µCode Linux Kernel 2.6.29
SW Challenges
• Multi-core complexity and core count explosion drives
up SW complexity
– Multi-mode operation mixes and matches SW tasks
• Disaggregation of former centrally managed resource
fractures system integration
– SoC resource manager for heterogeneous systems
• Exponential cost growth
– Non-differentiated SW must be provided at no cost by
Semi’s
– Development elapsed time exceeds life cycle of device or
electronic product such as a phone
Redefine EDA/IP
• For the EDA/IP Industry to grow it must address
SW growth opportunity
• Evolutionary: ESL as a language/tool to enable
earlier SW development
– Only addresses development elapsed time
– Synopsys has acted to capture inorganic growth
opportunities
• Revolutionary: SW tasks are abstracted from the
HW
– Through the use of machine-to-machine
communications
– Through the introduction of HW assist: SoC resource
manager
– Removes SW workload
System Design Considerations
• Direct mapping to various silicon vendors
– Architectural floor planner
– Persistency - design intent capture and re-entrant design flow
• Strong suite of IP libraries
– Re-usable
– Pervasive
– Non-competitive
• Resource management for:
– Error handling, protection mechanisms, system addressing,
QoS, power management
• SW virtualization layer between HW specific resources
and operating systems/applications
“The integration platform must subsume the
traditional design flow, rather than displacing it.”
(Alberto Sangiovanni-Vincentelli)
• Architectural Intent must be captured
– Persistence through the design/implementation hardware
flow must be ensured
• Architectural Intent must solidify the tool chain

– Verification: re-use from Architectural specification to
100% validation
• Architectural Intent must be transparent

– Machine to machine interactions for the millions of lines
required to describe the system
Beyond EDA Classic
Global Considerations
Geographical – Then and Now
• Massive Market shift in the last decade
– Europe system knowledge evaporating with massive consolidation, restructuring and
refocus as consumption moves to non European markets
• ST, ST-Ericsson, Nokia, NXP, Infineon all have undergone massive changes
– USA manufacturing has re-located or partnered with Taiwan
• IBM-Chartered-Samsung-ST
• TSMC-Intel
• AMD-Chartered-Global Foundries-ST
– Japan, Inc struggling to understand the roadmap for the industry
– Taiwan and China designing increasingly complex SoCs and complete systems
• Huge mistake to ignore US and Japan Synopsys Cadence Mentor

– Strategy must encompass and protect USA 48.5% 46% 46%
existing revenue streams
EU 14.5% 22% 33%
– Rifle shot approach to Europe
Japan 20% 18% 15%
– Strategic approach to Japan
Asia 17% 14% 13%
– Follow the complex curve in China,
Korea and India
Japan, Inc
• Struggling to understand where their electronics
industry is going
– Foundry technology too expensive
• Abandoning @ 40nm, going with TSMC?
– Manufacturing consumption over seas
• Japan’s value – still the leader in consumer electronics
– System expertise – consumer and automotive
– Content ownership
– System level market presence
– Cohesive action while maintaining independence
• INCJ approved funding to $8B (http://www.incj.co.jp/)
China Inc
• Moving up the food chain and
attacking electronic development
– World class innovators in 5 years
• Leveraging local consumption, local
standards and local manufacturing
– Dominating emerging markets (Latin
America, Africa, India)
• Challenging all cost assumptions in
the industry vendor chain
• Major developing area – opportunity to
shape thought process from ground
level
Cannot treat as simply a
“market share” opportunity
India Inc.
• India vying for the development of libraries and basic IP
– Virtually no fabless or SoC companies in India
– Focus seems to be standards based software, digital and mixed signal
IP
• Major players such as Wipro and HCL have sprung up design service
partners for IDMs and fabless semiconductor companies
– Emerging private label brands with complete systems engineering
• Most major US, European and Japanese semiconductor companies have
design centers in India
– Purchase decisions go through HQ
– Although as is the case at ST all Mixed Signal design is now India
• 50% of the cost of developing libraries and basic IP can be trimmed by an
Indian technology follower strategy (lagging the leader by 12 months)
Increasing ESD challenges for
IP Vendors and Suppliers
Stephen Fairbanks
Managing Director
sfairbanks@certus-semi.com
Certus Semiconductor
About Certus Semiconductor, LLC.

Certus Semiconductor is a cooperative corporation,
joining efforts of several of the worlds leading ESD and IO
designers, to bring to the semiconductor IP market a novel
support and service model in the area of ESD and IO
design. Along with the standard silicon proven ESD and IO
libraries in several technologies and foundries, Certus also
offers the world’s first “IO template” libraries, as well as
low cost, quick turn around and simulation proven custom
ESD and IO libraries; using unique device models based on
silicon proven designs that offer high confidence of first
silicon passing ESD standards. Certus also offers the
worlds best ESD strategies/devices for RF and III-V
semiconductor products.
www.certus-semi.com
Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential 24

ESD challenges in the IP Business
 A few realities about ESD

 We don’t usually sell ESD….it is never the product.
 Because of this no one wants to spend money or time on it.
 This also makes ESD protection an afterthought in many IP projects.
 Without ESD … manufacturing can be a very difficult process.
 Its hard to qualify the ESD impact

 ESD is usually one of the first suspects in a yield or field failure situation.
 If something fails in your customers assembly process, your ESD
performance can either be a liability or a saving grace when it comes
to customer relations and reputation.
 ESD can be a marketing difference between two competing products
Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential

 Increasing Challenges about ESD

 Advanced technologies nodes are producing transistors
and devices that are much more susceptible to ESD
failure than previous designs.
NMOS Failure Trends: Jedec

JEP157

Increasing Challenges about ESD

 Product Complexity is straining traditional ESD
design architectures
 Products routinely have >10 separate Power and Ground
Domains
 Blocks of different size and sensitivity are commonly
integrated
 PLL’s, RF, Analog, Audio, Sensors, Memories, SerDes
 New power sequencing and power down modes can
challenge traditional ESD architectures.
 These complexities lead to the situation where the
ESD performance of an IC is increasingly dependent on
chip level ESD architecture, as opposed to individual
IO and power domains.
This means that an IP block may pass ESD for one
customer’s product, but fail in another.
 Traditional IP block integration had all the ESD

protection residing in the Padring.
Example, here we have a network processor example,
where a High Speed SerDes IP block was integrated.
Traditional ESD was
handled by clamping the
ground together in the
padring. (shown by blue
arrows)
However, multitudes of
internal signals cross
block boundaries (shown
by red arrows)
Core failures on internal
signals are increasing.

 Traditional approach
for IP validation of ESD
is no longer sufficient.
 Focus beyond IO and
padring
 Internal Failures are

increasing.
 A result of greater
complexity and
integration.
Here is an internal buffer for a
signal between an RF
Transmitter and a digital core
that failed during CDM
stressing.
 There are a multitude of
techniques for
protecting internal
signals, one such
examples.
 Individual signal
protection:
 Pros:
– Very Effective
– Easy to Implement
 Cons: Individual Protection
Vdd1 Vdd2
– Big area increase
– Timing delay/skew
Input Output
Buffer Buffer
Vss1 Vss2
ESD Clamp in
Padring

 There are a multitude of
techniques for protecting
internal signals, one such
examples.
 Internal Clamp Placement
 Blue Squares represent
traditional ESD clamps found in
padring.
 Red Squares demonstrate that
with intelligently designed and
placed power and ground
clamps, internal signals can be
protected.
Pros:
No need for individual signal
protection
Cons:
Big area increase
Clamp design is not
straightforward
Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential Power Busses in core 31
 Concluding remarks:
 Bad Situations that strain business relationships:
 IP Vendor: A supposedly passing IP block fails in 1 customer.
 IP Customer: Product failures are in an IP block
 Failure Analysis: Is it the IP or the Integration?
 Debugging ESD problems is much harder than just avoiding them in the first place.
 Awareness of new and emerging failure mechanisms can help avoid them.
 IP Vendors: ESD design beyond the IO’s
 IP Providers: Expand ESD architecture beyond the padring.
As products increase in complexity and technologies

advance, expect to see ESD challenges continue to
increase. There will be an increased need for both IP
Vendors and IP Customers to be aware of these
increasing challenges and have methods in place to
address them.
Constellations Conference – Santa Clara
March 31st , 2010
www.tiempo-ic.com sales@tiempo-ic.com
TIEMPO mission
• Offer powerful asynchronous core IPs supported

by an innovative design and synthesis flow for low
power embedded electronics and secured devices
• Allow our customers to design chips with
outstanding performances in ultra-low power
consumption, speed and security against hardware
attacks
Contactless and other Ultra-low power Mobile consumer Automotive Aerospace

electronic transactions embedded electronics electronics
Copyright TIEMPO 2010 – March 31st , 2010 – Constellations Conference, Santa Clara
Agenda
• Introduction
• Tiempo technology benefits
• Tiempo IP portfolio
• Tiempo design flow
• Conclusion
Case study: contactless
applications
Ultra-low power Works at variable

with high voltage & remote
processing speed power source
High level of
security against Immediate wake-up
hardware attacks
Tiempo asynchronous design technology offers

breakthrough performances on all these aspects
Demo at “Cartes 2009” : Illustration of Tiempo
benefits on a PayPass™ Magstripe transaction
Smartcard with
1
standard chip
Smartcard with
Tiempo chips
2 1 2
TAM16 DES
• With Tiempo, the
processing & crypto
time is divided by 6
• PayPass™
Magstripe
transaction in 49ms
Proven breakthrough performances
• Breaking today’s barriers: on a

Paypass™ Magstripe transaction
• Transaction completed in less than
50ms
• Processing & crypto time divided by
6
• Total transaction time is reduced by
38%
• Breaking tomorrow’s barriers

• Contactless transaction are
spreading out to more applications in
the security conscious industry
• As more processing is required on
the card, processing performance
(with extremely limited power) is Smart Card Trends
now a key success factor Sept-Oct 2009 (Cover)
TIEMPO technology benefits
(1)
• Lower dynamic power consumption
• Lower energy consumption (/4)
• Lower current peaks (/15)
• Lower static power consumption
• Power gating at finer-grain level
• Cells optimized for lower leakage
• Works at lower voltage level /5
• Ex: 0.6V on CMOS 130 nm GP

• Works at variable voltage range
• Robustness against voltage
variations
/3
• Easy DVS implementation
• Immediate sleep & wake-up
• Transitions in a few ns instead of µs
TIEMPO technology benefits
(2)
• Lower noise, lower electromagnetic emission
• Adapted to systems with EMI constraints
(automotive, medical, aerospace)
• High performances
• Operators can work at maximum execution
speed
• Allows very modular designs (ideal for multi-
cores)
• Higher resistance to PVT variations
• Delay insensitivity allows better robustness
against process-voltage-temperature variations
• Ideal for advanced technologies (65 nm and
below)
• Higher resistance to hardware attacks
• Attacks using power analysis and fault injections
• Ideal for secured systems (smartcards, NFC)
TIEMPO technology principles
• Technology for the design of asynchronous and delay insensitive

integrated circuits
• Asynchronous = no clock at all
• Delay insensitive = functionally correct regardless of any delay in gates and
wires (no delay assumption)
• Allow designs with both ultra-low power and high performances
• Can be described with high-level models, in standard language
Asynchronous
Ack Hazard
delay Hazard
insensitive Data Free Free
(without clock, Req Logic Logic
without delay AReg AReg AReg
assumption)
Synchronous Data Reg Logic Reg Logic Reg

(with clock)
Clock
Agenda
• Introduction
• Conclusion
TIEMPO IP cores
• TAM16, asynchronous 16-bit microcontroller core
• With peripherals (UART, SPI, I2C, Timers, Int Ctrl..)
• With SDK and customizable instruction set
• Coming soon: TAM32, 32-bit microprocessor core
• Asynchronous crypto-processor cores
• PKA (Public Key Accelerator) for RSA & ECC
• AES
• DES/3DES
• All cores available with different options:
• Top-level asynchronous/synchronous interface
• Netlist secured against power/fault attacks
TAM16 + Crypto-
16-bit µC processor
cores
+ Security
TAM32 counter-
32-bit µP measures
TAM16 microcontroller core
• Outstanding power
performances
• Lower energy consumption
(divided by 4)
• Lower current peaks (divided by
15)
• Faster wake-up time (< 5 ns),
immediate sleep mode
• Power-efficient instruction set

• Easily programmable: 65 instructions and 7 addressing modes
• Fast and energy-efficient interrupt control and peripheral
communication
• Software Development Kit: assembler, linker, instruction set simulator,
C compiler and debugger (based on GCC/GDB)
• Instruction set can be easily customized

• To match de-facto industry standards
TAM16 microcontroller chip
• Silicon-proven IP core
• CMOS 130 nm GP technology
• Test chip fully operational
• With expected performances (speed,
energy consumption)
• TAM16 chip includes

• TAM16 core with peripherals
• 16 KB RAM, 1 KB ROM (3rd-party)
• BIST (412 instructions)
• Next silicon: run in Feb 2010

• TSMC CMOS 130 nm LP Power supply (Volt)0.7V 1.2V
• Asynchronous memories
• Multiple power domains Execution speed (MIPS) 6.1 11.8
• Minimal static consumption Core consumption37.2 47.6
(µA/MIPS)
Speed and power measurements on actual
chip
DES crypto-processor core
• Standard ciphering &
deciphering algorithms: DES &
3DES
• Outstanding power
performances
• Ultra-low power (energy &
peaks)
• Ultra-low noise/EMI
• High speed (no need for fast
clock)
• Secured option
• Protection against attacks
(power analysis and fault
injections)
• Two interface options Supply voltage 0.6V 1.2V
• Asynchronous 16-bit interface range
(use as TAM16
coprocessor) Max. current peaks 250 µA 800 µA
• Synchronous 8 or
16-bit interface Current consumption 200 µA 1 mA
(integration into DES execution time 2.3 µs 250 ns
sync. designs)
Performances measured on DES4 chip (CMOS
Copyright TIEMPO 2010 – March 31st , 2010 – Constellations Conference, Santa Clara 130nm GP)
AES crypto-processor core
• Standard ciphering & deciphering AES

algorithm
• Key: 128/192/256 bit
• Data: 128 bit
• Outstanding power performances
• Ultra-low power (energy & peaks)
• High speed (no need for fast clock)
• Two mode: priority on performance or power
• Secured option
• Protection against attacks (power analysis
and fault injections)
• Top-level interface choice

• Asynchronous interface (use as TAM16 co-processor)
• Synchronous interface (integration into synchronous
designs)
Public key accelerator
(RSA/ECC)
• RSA & ECC accelerator
• Key: up to 2048/4096 bit
• Int/Mod operations
• Specific functions (FSMs)
• Primitives for ECC & RSA acceleration
• Outstanding power performances
• Ultra-low power (energy & peaks)
• High speed (no need for fast clock)
• Secured option
• Protection against attacks (power analysis
and fault injections)
• Top-level interface choice

• Asynchronous interface (use as TAM16 co-
processor)
• Synchronous interface (integration into
synchronous designs)
TAM32 microprocessor core Work in
progress
• Applications: low power & high

performance embedded Instruction
electronics memory
• Mobile consumer electronics

• Outstanding power performances Fetch
• Lower energy consumption

(divided by 2) for Register File
Memory, debug, coprocessor

equivalent
or higher speed (> 400 MIPS
on CMOS 65 nm Multiplier Shifter
LP)
Decode
• No PLL required (less power) ALU
• Lower current peaks (/15)

Load/Store Branch
• Fast wake-up time (< 5 ns) and
immediate sleep mode
• Roadmap driven by partnerships Data memory
Agenda
• Introduction
• Conclusion
TIEMPO Design Flow
• Specific synthesis: Asynchronous Circuit Compiler (ACC)
• Fully-automated synthesis tool for asynchronous design
• Using standard hardware description languages
• Input: TLM-like descriptions in SystemVerilog
• Output: gate-level netlists in Verilog
• Using standard cell libraries
• Complemented (by Tiempo) with optimized asynchronous cells
• Available with IP license or design service
• Standard design flow: use of industry-standard tools
• SystemVerilog models can be simulated with any HDL simulator
• Easy simulation of mixed asynchronous/synchronous designs
• Implementation with industry-standard P&R and STA tools
• Easy implementation of mixed asynchronous/synchronous designs
• Asynchronous/synchronous interfaces automatically generated by ACC
TIEMPO flow for mixed
asynchronous-synchronous design
Verilog/VHDL RTL
Synchronous part
SystemVerilog
TLM
Asynchronous part
Verilog, VHDL,
HDL Simulation SystemVerilog
ACC RTL Synthesis , SystemC,
VMM / OVM Testbenches
Verilog Gate-level
Synchronous part
Verilog Gate-level
Asynchronous
part Standard tools
Tiempo tools
Place & Route STA Asynchronous-

synchronous
Interfaces
Use of standard tools to
simulate/debug Tiempo asynchronous
SV models
SV asynchronous model : FSM example
module FSM (
push_channel_opcode_t.out OP, // Control ALU operation type
push_channel_event_type.out ST, // Specifies that opcode has been sent to ALU
push_channel_go_t.in GO, // Starts FSM and selects sequence of actions
push_channel_bit.in AB // Abort signal (return to initial state S0)
);
always begin : fsm_process // Unique process implementing the fsm
go_t go; bit ab; opcode-t op; state_t state; // local and state variables
unique case (state)
S0: begin
GO.Read(go);
unique case (go)
SEQ1: state = S1;
SEQ2: state = S2; AB = 1 AB = 1
endcase S0
end GO = GO =
S1, S2: begin SEQ1 SEQ2
unique if (state == S1) op = ADD;
else op = SUB;
AB.Read(ab);
S
unique if (ab == 1'b1) state = S0; S2
else begin OP.Write(op); state = S3; end 1
end
S3: begin
ST.Write(SREVENT); state = S0; AB = 0 AB = 0
end
endcase
end
endmodule S3
SV asynchronous model : ALU example
module ALU(
push_channel_byte.out Z, // ALU output
push_channel_byte.in A, // ALU first operand
push_channel_byte.in B, // ALU second operand
push_channel_opcode_t.in OP // Control signal to define computation type
);
always begin : compute
opcode_t op; byte a, b, z; // local variables
fork
OP.BeginRead(op);
A.BeginRead(a); A B
B.BeginRead(b);
join
unique case (op) // computation phase
ADD: z = a + b;
SUB: z = a - b;
endcase OP
Z.Write(z); // output update
fork ALU
OP.EndRead();
A.EndRead();
B.EndRead(); Z
join
end
endmodule
Agenda
• Introduction
• Conclusion
Conclusion
• Tiempo innovative design technology offers

significant gains in
• Ultra low power consumption
• Processing speed in power constrained
environments
Contactless and other Ultra-low power Mobile consumer Automotive Aerospace

electronic transactions embedded electronics electronics
• Tiempo asynchronous synthesis flow is

integrated into standard design flows
• Standard language, simulation and back-end tools
Turn Your Engineering
Cost Center Into an IP
Profit Center
© IPextreme, Inc.
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Complete IP Delivered to the Desktop
Complete IP Package IP Distribution and Support Portal
Integration
Tests
Source Code
Secure Access
Expert Configuration
EDA Scripts
Support
Support for Major

Full Documentation Issue Tracking
Software & Industry EDA Flows
Drivers

Our Famous IP Partners

Company Fact Sheet
Company
 Semi IP licensing specialists
 Worldwide presence
• Corporate offices in technology centers
• Representatives in major regions
• Customers in more than 20 countries Germany Japan
 45+ titles in our portfolio Silicon Valley Israel Korea
India Taiwan
China
Technology
 Strong IP business, design, and
methodology experience
 Patent pending Xpack IP packaging,
repository, distribution, and support
system
Business
 100% focused on IP licensing
Awards
 2008 Gartner “Cool Vendor”
 2009 Red Herring “N.A.Top 100” Silicon Valley Munich Tokyo

Leveraging Your IP
Assets
Integrated Solution for IP

Packaging, Distribution and
Support
© IPextreme, Inc.
Increase the Value of Your Designs
Design Life Cycle

$
Revenue
Extend the Life And
Value of Your Designs
Enter new
markets
Reuse Your
Design on
Future Projects
Retain integrating
customers & manage
end-of-chip-life
Chip
Early Peak Late

The IP Challenges
Packaging IP for ease of use and ease of support

 Preserving the original designers knowledge
 Consistency in IP delivery package
Knowing what IP is available
 What IP have we developed?
 What IP have we purchased?
Tracking usage of IP
 Who is using the IP?
 What revisions are being used?
 Notifying users of updates
Tracking internal usage of IP licensed from IP vendor
 Ensuring all licensed IP is being used legally
Distribution of IP to users
 Controlling who receives IP
Supporting IP users
 Tracking issues across various IP teams and internal users
 Monitor support costs for each IP

IP Packaging Requirements
Requirement Solution
Ease of Use Standardized IP format for a
consistent look and feel
Low Support Cost Package IP with Designer’s Intent

and Knowledge

IP Database Requirements
Centralized storage of IP IP Database
Users easily browse available IP Organized IP Catalog
Users easily find specific IP IP Search Engine

IP Distribution Requirements
Control who can access IP IP access management
Know who has/is using the IP IP access tracking
Easy communication to users User contact management
Security for IP access Secure IP distribution
Security for IP support Secure file sharing

IP Support Requirements
No lost support requests Support tracking system
Ability to easily find the right person Support ticket routing
Easy communication to IP users Automated distribution of IP bulletins
and change notices
Ability to analyze support cost Support hour tracking
Low IP support cost IP support knowledge base

IP User Requirements
Ease of Use Common look and feel
Minimize errors and support cost Self checking parameter settings
Support for all EDA flows Automated EDA script generation

XPack™ IP Management System
Fully Integrated IP Packaging, Repository, Distribution and Support System
IP Repository IP Access & IP License Secure Web Customer

& Search Tracking Control Distribution Support
Advanced Search

Examples of IP we have
productized

Support
© IPextreme, Inc.
IP Commercialization Activities
Activities
Partner
Design Preparation
Packaging
Marketing
Sales
Legal Contracts
Distribution
Support
Maintenance
Revenue Collection
Royalty Reports & Collection

Industry-leading Soft Processors
8-Bit Family 16-Bit Family 32-Bit Entry Level 32-Bit Mid-Range 32-Bit High-End
8-15K gates 40-90K gates 40-100K gates 100-200K gates >200K gates
ColdFire ColdFire
ColdFire ColdFire
v2
32-BITAMBA4-StgeNEXUS v4
32-BITAMBA9-StgeNEXUS
DSP DSP MMU
HC08 C166 Power Arch Power Arch Power Arch
HCS08 C166 v1 e200 z0 e200 z3 e200 z6

8-BIT BDM 16-BITFPI 4-StgeOCDS 32-BITAMBA4-StgeNEXUS 32 BITAMBA4-StgeNEXUS 32 BITAMBA7-StgeNEXUS
MMU DSP VLE Only VLE MMU FPU DSP VLE MMU FPU DSP
8051 CR16 ColdFire Power Arch TriCore
M8051 CR16CP ColdFire e200 z1 TriCore1

8-BIT 2-Cyc DBG 16-BITAMBA3-StgeNEXUS v1
32-BITAMBA4-Stge BDM 32 BITAMBA4-StgeNEXUS 32 BIT FPI
DSP
4-StgeOCDS
FPU 3 Pipe
DSP VLE MMU

AMBA Peripheral Library
Library of 20 AMBA 2.0 Peripherals

All proven in high-volume National Semi Products
Low-cost, royalty-free
Processor
RAM (32-Bit AHB Master)
AMBA
RAM Controller DMA Controller AHB Backbone
Library
AHB System Bus
Multi-Input Real Time Timing and AMBA AHB-to-APB

Interrupt Smart Card Versatile
Wakeup Clock Watchdog Watcher Bridge
Controller Interface Timer Unit
Module Module Module
APB
Peripheral Bus
AccessBus/ Advanced General General I2S Enhanced

MICROWIRE/
I2C Full-CAN Audio Purpose Purpose I/O Audio Multi-Function
SPI Interface
Interface Interface USART Ports Interface Timer

#1 Automotive IP Portfolio
Automotive IP Lineup
Controllers Power Architecture
CR16
C166
TriCore
Networking FlexRay
CAN
Debug Nexus5001
MCDS
CJTAG 1149.7
Serial MLI
Interfaces MSC
Horizontal Peripherals

USB20Hub IP Features
Cypress USB market share leader USB HUB
Proven in Cypress EZ-USB HX2LP™ 12 Mbps LS USB

1.5 Mbps
family of Hub chips Serial
Interface
Engine
Transaction
Translator
Device
(SIE) (TT)
USB-IF and WHQL certified 12 Mbps

FS USB
Device
HS USB
Configurable: Traffic
480 Mbps HS USB
ci goL gni t uo R
480 Mbps Device
 2-7 downstream ports
tr o P maert s p U BS U
Hub Repeater
 Single-TT to minimize size or 480 Mbps

HS USB
Device
 Multi-TT for max FS throughput

 Once implemented via EEPROM
Multi-TT USB HUB 12 Mbps
Supports high, full and low speed Transaction
Translator
(TT) LS USB
1.5 Mbps
Ultra-low power, runs on Bus Power Serial

Transaction
Translator
Device
Interface (TT)
Low gate count, small die size HS USB

Engine
(SIE) Transaction
Translator
1.5 Mbps
LS USB
Device
(TT)
Full hardware implementation, no

Traffic
Transaction 12 Mbps
FS USB
ci goL gni t uo R
Translator Device
firmware or microcode
tr o P maert s p U BS U
(TT)
480 Mbps
Configurable once implemented via

FS USB
12 Mbps Device
Hub Repeater
external SPI EEPROM

IEEE 1149.7 CJTAG
Industry’s First CJTAG Core
 Provides increased functionality to embedded
designs over the IEEE 1149.1 standard
 Endorsed by IEEE and MIPI standards
organizations for next generation test and debug
Supports IEEE 1149.7 classes 0–5 (selected

through hardware configuration parameter)
Partitioned along IEEE 1149.7-specified

functional boundaries (so that only the
required hardware is included):
 Extended Processing Unit (EPU) for class 0–3
operation
 Advanced Processing Unit (APU) for class 4–5
operation
 Further partitioning within EPU and APU for class-
specific and optional features Deliverables
 Separate blocks for clock and reset signal  Synthesizable source code
conditioning  Integration testbench and tests
 Documentation
Supports all mandatory and optional scan  Scripts
formats: JScan0–3, SScan0–3, OScan0–7, • Simulation and synthesis
and MScan • Support for common EDA tools

BlueMoon 2.1® Bluetooth 2.1+EDR
BlueMoon Block Diagram Highlights
Single core Bluetooth solution

Link Controller Baseband Radio
GPIO
PCM PCM Power

Management
Output
Power
 Integrated RF, Baseband, Firmware (ROM-able)
Control
 Connection to host via standard HCI UART
HCI UART
Tx Tx Bluetooth 1.2, 2.0 + EDR & 2.1 + EDR compliant
 Firmware upgradable to Bluetooth 3.0
ROM
32-Bit CPU
BT
DSP Enhanced Data Rate
Firmware
 Throughput >2Mb/s (3Mbps modulation)
RAM
Rx Rx Compatible with all 3rd -party Bluetooth applications
 Through standard HCI software interface
Advanced features for enhanced audio quality
Firmware in integrated ROM for lowest cost
 Patch RAM area for easy firmware upgrades
Roadmap for Bluetooth Ultra Low Energy
Main Features
 0.13 µm standard CMOS (UMC)  HCI interface UART alt. 3-wire, up to 3.25Mbaud
 RF amplifier output max +7 dBm at package pin  Dual PCM audio interface ( I2S mode, A-law, µ-law, Linear )
 RF sensitivity -89 dBm(BDR) @ 0.1 % BER  3-wire WLAN Coex interface
-91 dBm(EDR) @ 0.1 % BER  Control lines for external Class-1 PA
 Clock input 26 MHz
 32kHz Low Power Clock input (optional)

Summary

Support
© IPextreme, Inc.
XPack - IP Management System
Packages IP for reuse

 Packages designer knowledge with IP
 Consistent look and feel with configuration GUI
 Automated EDA script generation (EDA tool neutral)
IP database cataloging and search
License Management prevents unauthorized usage of IP
Secure IP distribution and secure file sharing
Complete support infrastructure to lower support costs and
accelerate resolution of support requests
Configurable and customizable to match your company’s
precise requirements
Packages and manages IP assets for higher
productivity, lower cost and lower risk
IP Portfolio
32-bit Microprocessors Debug
 Freescale Coldfire v1, v2, v4  Texas Instruments 1149.7 CJTAG
 Freescale Coldfire v1 for Altera Cyclone III
 Freescale Power Architecture
 Infineon Tricore Cypress USB 2.0 Hub
16-bit Microprocessors Infineon BlueMoonTM Bluetooth 2.1+EDR

 Infineon C166
 National Semiconductor CR16  IP Licensing
 BlueMoon Die
8-bit Microprocessor
 Mentor Graphics M8051 Automotive
 Freescale HCS08  Freescale FlexRay
 Infineon MultiCAN
AMBA Interfaces  Infineon Microsecond Channel
 USART, I2S, I2C, AAI, Microwire, CAN  Infineon Multiprocessor Link Interface
AMBA System Functions Technology Licensing

 Interrupt Controller, DMA Controller, RAM  Motorola Digital Clock Generator
Controller, Timer & Watchdog, Timers RTC
• PLL Replacement
 Infineon Multicore Debug System
• Automotive multiprocessor debug system

IPextreme Summary
World’s Leading Supplier of Production Proven IP from Leading IDMs
IP and Design Reuse technology and expertise
100% focused on semiconductor IP
Please let us know how we can help

Welcome to the Future – Start Running
Thank You!!!
Every morning in Africa, a Every morning a lion wakes It doesn’t matter whether
gazelle wakes up up you are a lion or a gazelle
It knows it must outrun the It knows it must outrun the When the sun comes up,
fastest lion or it will be slowest gazelle or it will you better start running
killed starve
– African proverb
Business Model Panel

hathawjo [printed: August 1, 2007 8:54 AM] [saved: August 1, 2007 8:56 AM] C:\Documents and Settings\hathawjo\Local Settings\Temp\07071W020_NVTV Ratings Agency Pres_TEMPLATE_2 (2).ppt
Turn-key IP Block to
Simplify AMBA-based
SoC Designs
87
Sonics – Company Introduction
Sonics RS CV34 1-7-08 CF-DJ Notes & Grfx Updates 1PM
• Sonics set out to solve the biggest Licensees
problem facing the SoC industry:
Ever increasing design costs.
• Sonics has succeeded in dramatically

lower design costs by developing highly
configurable IP for the on-chip
communications networks that enable
the design of complex chips.
• The world’s leading companies have

turned to Sonics for their most
demanding SoCs designs, and in turn
they have sold more than 750 million
chips based on Sonics’ IP.
• Sonics has invested over $65 million to OEMs

develop its unique IP, resulting in more
than 50 patent properties.
• Sonics is the Number 1 global provider

of on-chip communications network IP.
88
Sonics Network for AMBA Protocol - Product
Overview
Sonics is addressing the industry problem of building SoCs that have an
increasing number of heterogeneous cores with a fast and reliable methodology
• SNAP is the first turn-key product on the market that turns a multilayer AHB
design into an IP block
• Ideal for Embedded SoCs with a large number of IP cores having AHB and APB
interfaces but also contain other interfaces like AXI and/or OCP
• Product is optimized for low-gate count
• Simple to use tools that require little or no training along with a unique ‘client-
server’ model to reduce cost
• Reduces customers’ development cost - not wasting engineering resources on
complex multilayer design
 Design time is reduced from months to days!
 ‘Good by design’ IP reduces test and debug time
• SNAP is ideal for Embedded SoCs for in the follow market segments:
• Wireless communications: 3G/4G basebands, WLAN, WiMax
• Wired communications: Home gateways, wireless routers
• Consumer electronics: PMP, MP3
• Automotive: Control, Telematics
89
SNAP High-Level Architecture
• Replace traditional bus with

advanced on-chip Network:
– Interconnect Matrix
– AHB Masters Layers
– AHB/APB Branches
• Data Flow services
• Decoupled socket based
architecture
• Power Management
• Memory scheduler (optional)
90
You are Ready for SNAP when…
Your SoC Connectivity is growing in

Complexity:
Simplify Your Design:
• Increasing number of cores with new and legacy
interfaces • No need to worry
• Reaching the limits of AHB bus performance about clocks,
• Increased engineering resources needed due to the arbitration, bus widths
shortcomings of existing bus design tools and or data formats
methodology
• Evolving designs to incorporate faster processors • Provides protocol
• ARM AXI processors translation
• MIPS AHB, OCP processors • Reduce wire
• Re-architect designs to optimize for low power congestion
• Hitting the Memory Bottleneck • Provides clock
• AHB designs have a bottleneck at the memory port division bridges
• Lack of concurrency and frequency limit the solution
• Allows engineering
innovation for value-
added functions
91
SNAP Features
• Hubs
(aka interconnect matrix, crossbar,
exchange):
• Provide dedicated connections
core
between agents embedded in the core core
hub. SNAP allows two hubs per

design which can be connected
through a pipeline point
• Layers
• Allow multiple masters to be
connected to a single hub port
• Branches slave slave slave
• Allow multiple slaves to be

connected to a single hub port
92
Client-Server Interaction
Overview
• Simple and free download of the SNAP Capture
tool – No tools purchase necessary
• Users configure their designs using the
snapCapture GUI
• User uploads design to SNAP Server SNAP Server
• The SNAP Server then sends back RTL,
synthesis scripts, and test bench.
• Server keeps track of user ‘credits’
Internet
Internet
Company A
Company B
SNAP Client owner
SNAP Client Owner

… …
SNAP Client N
SNAP Client 1
SNAP Client 1
SNAP Client 2
93
SNAP Design Capture
• Interface Overview:
Tool Bar
Design
SNAP Window
Components
Configuration Quick
Tabs Help
94
Sample SNAP Design - Overview
Set Top Box • SoC Design Features

• 19 Masters
• CPU subsystem, DSP
subsystem, Video
subsystem
• 39 Slaves
• Audio, USB, Storage,
Memory
• System Speed: 200MHz
95
Sample SNAP Design – System Block Diagram
96
Sample SNAP Design – SNAP view of block diagram
VBE
VFE
EDMA
DS ARM9D ARM9I SATA
P
hubLL hubSYS
sram ddr2
ocp
COMM
Storage
axi
ApbSb0
ahb
SYSC
SIO
apb 97
Sample SNAP Design – SNAP GUI Design Capture
98
Sample SNAP Design – By the numbers
• Frequency
• Target: 250MHz
• Synthesis: 465MHz
• Synthesis (w/ 30% margin):
325MHz
• Area
• TSMC 65G: 146K gates 146K gates
• Only 2500 gates / core
• Cost to add additional…
• AHB Master layer: 900 gates
• AHB Master: 1000 gates
• AHB Slave branch: 1500 gates
• AHB Slave: 100 gates
• APB Slave branch: 20 gates
• APB Slave: 45 gates
99
Summary - Benefits
• Increased design productivity – multilayer interconnect is one

IP block with easy to use GUI
• Seamless upgrade path from a multilayer AHB architecture
• Superior performance, power, and area than competitive solutions using
AXI matrix + AHB buses
• Ultra-low power with Automatic clock gating
• High performance
• Cross-bar structure, separate request / response network
• AHB multi-ports agents: up to 8x the bandwidth of an AHB bus
• Supports all popular interfaces
• Does all the protocol, data width and clock conversions
• No need for bridges
• No stand alone validation required
• Lowest risk - Fully verified IP
100
Sidense
Non-Volatile Memory IP
March 31, 2010
Company Profile
Name: Sidense Corp. - Private
Founded: September 2004
Headquarters: Ottawa, Canada
Offices: USA, Japan, Korea, China, Taiwan, and
France
Product: One-time-programmable (OTP) antifuse-based
non-volatile memory (NVM) targeting standard-
logic CMOS processes
Employees: 40+
Customers: 80+ customer designs
Patents: Over 60 patents issued or pending
102 The Future of Logic NVMTM

Embedded NVM Landscape
32nm
40nm Mask
ROM
Process Complexity
65nm
eFUSE
90nm 2T
NVM
130nm NOR
Flash
Floating
180nm Gate
Low Scalability challenges High

A Better NVM Solution

Target Markets and Applications
HD Set-top Boxes HD recorders
RFID Tags RFICs
Implantable devices
Micro-controllers
Automotive ICs Smart Phones
Military/Space
Hearing aids
Timer chips
Industrial Equipment
Configurable Processors DVD players

The Sidense Edge (Top 5 Reasons)

Smallest Bit Cell – 1T Split-Channel
WL
Program Area
BL
BL
1T- Fuse ™
™ Gate Oxide
IO Oxide
LDD
N+
N
Channel ISOL
The only reliable 1T architecture

Broad Foundry and Node Support

Technology Flexibility
512bits
x16 eMTP
SiPROM - 64 Kbits (4Kx16)

4 Kbits x2
Fast Read
dr o wK 1
16 Kbits
Single-cell
dr o wK 1
32 Kbits
Mask ROM
s dr o wK 2
16-bit IO

Highly Secure – Code and Data
Bit 1 Bit 2

Most Reliable Bit-Cell Architecture

SiPROM – High-Density NVM

SLP – Very Low Power NVM
VDD
VRR
VPP
VSS
WE PGM / Verify CTRL
MODE
PGM CTRL
A F - PROM
OTP
CLK IO SHIFT
Latch REG
SEL, OE
Q
D
Summary

Can You Trust
Your IP Vendor?
How Not to
Lose Sleep
Over it
Hal Barbour
President, CAST, Inc.
IP Horror Stories
 We all hear about the “bad IP” news

 Unfulfilled promises
 Missed deadlines
 Poor quality code & materials
 Lousy support
 IP companies have come and gone

 Amphion
 inSilicon
 Dozens of smaller companies
Constellations Seminar — slide 116

Trust is a Key Factor
 Even the best IP will present some technical challenges
 What matters most is if you can trust the provider to help
you make it work
 External, commercial IP vendor
 In-house, IP & reuse group
 But how do you judge trustworthiness in advance?

 A matter of continual style, not a simple check-list
 Every organization has it’s own style, just like an individual’s
personality
 There are some critical things to look for …

First Impressions Matter
 Do they freely provide important information?

Can you:
 Download datasheets without registering?
 See sample ASIC & FPGA implementation
results (Fmax, resource numbers) without asking?
 Does their paranoia get in the way?
 Do they require an NDA for basic technical info?
 Do they demand an NDA for price info?
 Do they waste your time?
 Are you buried in marketing fluff?
 Will they quickly get you tech docs,
design specs, etc.?

Can They Run with You?
 Is the organization geared towards rapid,
effective response?
 What is their process for responding to technical
questions?
 Do their engineers seem as good as yours?
 How do they deal with
time zone differences?

Can They Deliver What They
Promise?
 Do they they know how to productize IP
for easy reuse?
 Do they have a track record of
financial success?
 Are they profitable? Any short-term
investor pressure?
 Is IP critical to their success (or design services)?
 Will they give you customer references?
 Don’t go by published “testimonials”
 Ask for — and talk with — engineers who have already
used the IP you want
Do They Understand System
Integration?
 Do they help make sure the IP is best for

your specific project?
 Most problems with
a core are really
problems understanding
the application and
designing the system correctly

System Integration Example
 Challenge:
 Need means for customers to
try complex compression
technology
 Enable evaluation with own
media, algorithm & core
study, system dev head start
 Solution:
 H.264/JPEG 2000 Reference
Design Platform
 Multiple CAST cores
 FPGA Prototyping Board
 SW GUI for Parameters &
Control

Licensing & Sales Issues
 Does the licensing meet your needs?
 Straight forward and adequately flexible
 Doesn’t bury you in legal minutia
 Is the pricing competitive?

 A good value for you
 A reasonable business
model for them
(you want the vendor
to stay alive)

Post-Sales Trust
 Do you seem to matter as much after the sale
as before?
 Do they have highly-commissioned
salespeople who are now
on to their next deal?
 Is their Support Organization
effective?
 Would you buy from
them again?

CAST Knows About Building
Trust
 Successful IP provider,
developer, and partner
 Sixteen years experience with IP
 Continually profitable, no debt
 Privately held, financially stable
 Unique market approach

 We only do digital IP,
designed for reusability
 Independent of semiconductor
technologies and EDA tools

CAST Knows About Building
Trust
 Effective Virtual Organization
 Global team of ~100 people:
stable, long-term partnerships
 24/7 culture with very fast response
 Always online with Email, IM & Skype
 Original developers available to
help with support
 Experience with diverse customers
and applications
 1,000 sales to over 600 customers
 Pre-sales help in selecting the right IP
 Post-sales support during system integration

Broad IP Product Line

CAST IP Highlights
 8051s — the fastest and smallest available versions,
from the largest independent supplier
 H.264 — the highest-quality 1080p Baseline video encoder
 Image Compression — the most choices, JPEG to JPEG
2000
 PCI Express — easy system integration with application
interface
 USB — a complete family of solutions
 Memory Controllers — advanced IP for DDR, NAND Flash,
SD, SDR mobile
 System IP Solutions — pre-integrated cores and software
for a system design head start

Conclusions
In judging IP provider trust:

 The quality of the people and character of
the company can ultimately be as
important as the product
 Choose wisely,
and get some sleep!

Selecting the right HD Video
IP for Multimedia
Applications
Chips&Media, Inc.
Market Outlook
Market Outlook
Multimedia Market Opportunities Unit : Million unit
HD Home CE Market
338
292
226
128
97
69
45
Source : iSuppli, In-Stat, Futire Horizons , C&M
Page 132 Confidential

SoC Technology Challenge
Increasing Complexity and Time to Market Pressures drive

SoC Challenge
Users Expectation Rapidly

Rising Complexity in SoC Design
Changing
 Rich multimedia experience  Increasing number of cores
 Computing functionality  Gigabits of frequency
interfaces
 Wireless connectivity options
 Increasing process variability
 “Always ON”
 Exploding data volume
 Compact and light design
 Low power modes
 Small foot print

In-House vs 3’rd party IP
Buying IP is main stream for designing Mobile System-

on-Chip(SoC)
In-house vs. Third-Party Multimedia IP Market Share for 2009
Note : Includes the use of any 3rd party Intellectual Property for graphics, audio or
video
Source : In-Stat, 9/09

Selecting Good Quality IP
Selecting Good Quality IP for Multimedia
Die size(mm2) / Cost($)
Performance
Multi-standards (MHz)
Bandwidth management Power (mW)

(MB/s)

Die Size (mm2) & Cost ($)
Silicon cost – driven by die

size
Boda7503
Boda7503
BIT Processor
MJPEG Boda7503-MJPEG
- RV
AMBA BUS
- VC1
- AVS
H.264 MPEG2 MPEG4 VC-1 DivX
- H.264
RV H.263 WMV Spark AVS -MP4
6.0mm2 in TSMC 90G with 200MHz cclk Logic gate count can be reduce by pre-
Including 2.0mm2 Internal SRAM configurability of decoding format according to
target applications

Performance (MHz)
High performance video processing

 Higher clock rates mean higher power
Clock required
133MHz
60MHz
20MHz
Resolutio
n
Boda7503 decodes H.264 HP up to 1080p 30fps at 133MHz

Performance - Latency Resilience
High Memory Latency

Tolerance
 Minimize the effect of memory latency on decoding performance
 # of Cycles (decoding H.264) vs Memory Latency
Higher bandwidth requirements
Lower bandwidth requirements
Boda7503 decodes in time

– even if bus latency approaches 200
cycles
0 100 200 300 500 access
Memory
latency(cycles)
Power Consumption (mW)
Active management of dynamic and leakage power

 Clock gating scheme
: Clocks can be shut down from blocks currently not needed
Saving power using Clock

gating from 17%~ 30%
Boda7503 uses multi-level clock gating to lower power consumption

Bandwidth Management - Bandwidth requirement(MB/sec)
Problem
 Preventing memory bandwidth congestion may be challenging with HD

resolutions.
 Additional SRAM may reduce an amount of bandwidth, but increase SOC size.
2D smart cache
 Smart algorithm of cache control will make significant bandwidth reduction,

with a little sacrificing in die size
 An optimized mapping configuration to store data (i.e H.264 pixels) into
external memory decrease the transfer amount between the decoding unit
and the memory.

Bandwidth Management - Bandwidth requirement (MB/sec)
cont’
Tiled memory map

 Alleviate the BUS traffic congestions by 20% by increasing efficiency of bus
utilization
Boda7503_Linear 64b-
Boda7503_Tiled 32b-
SDR@c=266,a=266 DDR2@c=266,a=266
Taken from the 100 frames of the clip “AVC=MP

Allegro_BdWidth_CABAC_01_L41_HD”

Multi-standards
Extensive Multi-format Video Support to Enable the MORE

 Enables MORE adaptable
 Enables MORE adaptable devices
districts
Mobile
 Common format
H.263
• H.264, MPEG-4, MPEG-2
Blu-ray DTV/STB  Popular format by

district
• KOR : DivX
• CHN : RMVB, AVS
• US : VC-1
Portable

Multi-standards cont’
Boda7503 supports multi-codec in a single core
Format
Application Internet Portable Mobile DTV STB DVD Security
streaming
H.264 O O O O O O O
VC-1 O   　 O  　
WMV9 O O 　　　 O 　
H.263 　　 O 　　　　
MPEG-4 O O 　　　 O O
DivX O O 　　　　　
MPEG-2 　　 O O O O 　
AVS 　　  O O  　
RMVB O O 　　　　　
Sorenson O 　　　　　　
MJPEG 　　　　　　 O

Chips&Media Solution
 BODA/CODA video codec hardware blocks provides :

 Cost-effective small gate count
 Full HD decoding/encoding at lowest power
 Lowest bandwidth with high latency tolerance
 Multi-codec supported covering broadcasting, web or PC contents
Confidential
Selecting Verified IP Provider
IP-provider Selection Criteria
Selecting Verified IP Provider by Assessing the Risk of

Failure :
Does the company have a history of commercially manufacturing the IP?

⋅ Customer references
⋅ Silicon-proven and market-proven experiences
Does the company have the experience and support level you need?
⋅ Standard documented design support
⋅ Dedicated R&D engineers involved in support
Does the company develop all IP deliverables itself?

⋅ Technology leadership
⋅ R&D expertise and practices
Does the company have clear strategy to keep long-term partnership?

⋅ Financial records enough to maintain
⋅ Competitive product/technology roadmap

Summary
What does Chips&Media Deliver?
 The Best-in Class IP

 Best class performance
 Power and silicon area leadership
 Rich video decode and encode IP portfolio
 Complete & Reliable IP

 Fully-verified IP deliverables
 Worldwide +40 customer references
 Over 70 consumer devices powered Chips&Media’s technology
 Strong support capability

 Dedicated technical support with rich experience in the field
 Fast and in-depth support service via ticketing system
 Complete product roadmap

 Continuous investment in employees and technologies
 Competitive roadmap to response for the most market requirements

Q&A
philip.han@chipsnmedia.c
om
Afternoon Break
20 Minutes
Slide 150 Slide 150

Ultra Low Power CoolFlux DSP Cores
Sweetening Your Green Chip Dreams
Licensable for SoCs, ASICs & ASSPs Bringing Affordable
Ultra Low Power DSP Performance to your Chip Designs
Constellations Event, March 31st , 2010

Overview
CoolFlux success stories in Audio and 4G Basebands

Ultra Low Power Performance Design
Cool Technical merits for Green Chips
Application Software and Development Tools for high productivity
Conclusions
© NXP B.V. 2010

152
CoolFlux Success Stories
Cool References to CoolFlux DSP

– DSPFactory, (now part of On Semiconductors)
licensed CoolFlux DSP for their ultra low power
hearing aid chips
– Phonak, licensed CoolFlux DSP for their ultra
low power digital audio hearing aid
communication system
– Cochlear, licensed CoolFlux DSP for next
generation Hearing Implants
– Other known users of CoolFlux DSP are
Renesas and NXP next to 2 undisclosed global
2008 top 10 semiconductor companies and many
other fabless semis and system companies.
Cool Application areas
– CoolFlux DSP is used in chips for Headphones
and Headsets, MP3 players, Mobile Multimedia,
Blue Ray players, Wireless Audio, Car Stereo,
Digital TV … any embedded audio subsystem is
candidate
– CoolFlux BSP is used in chips for WiMAX and
multi-standard software defined radio basebands
chips for emerging 4G standard LTE
© NXP B.V. 2010

153
CoolFlux DSP/BSP Design Goals
Domain:
– CoolFlux DSP: Audio,
– CoolFlux BSP Software Defined Radio & Wireline Basebands
Ultra low power consumption
– Well balanced with good performance and low gate count
– ULP techniques used throughout the design hierarchy like
• Clock gating
• Operand isolation
• Locality of reference
Programmable in ANSI-C
– Highly optimizing and efficient compiler
– More maintainable and shorter SW development schedules, without loss of quality
Small core, small memory footprints, minimizing dynamic and static power
Core to be usable:
– Stand-alone mode (including control)
– Coprocessor for microcontroller
– Multi-core, also to cool down chips: reducing voltage and clock through parallellism
© NXP B.V. 2010

154
CoolFlux DSP architecture
24/56 bit data paths (CF6-24)
2x 24x24 bit multipliers
2x 56 bit ALUs + 1x24 bit ALU
4x 56 bit accumulators
JTAG debug interface (multicore)
8 Operations in parallel per clock
cycle
© NXP B.V. 2010

155
CoolFlux BSP Architecture Enhanced for
Baseband Signal Processing
All 24/56 bit data paths of CoolFlux DSP
usable backwards compatible at C-level
24 bit addressing
PLUS:
Modes for Complex Arithmetic and SIMD
8x 12x12 bit multipliers
4x 12/28 bit ALUs + 2x12 bit ALU
4x 28 bit dual accumulators
Instruction enhancements for FFT and
Viterbi
RESULTING IN e.g.:
20 Operations in parallel per clock cycle
2 cycle complex butterfly Radix-2 FFT
level performance
© NXP B.V. 2010

156
CoolFlux DSP – Cool Well Balanced Results*
Small core:
– 43kgates + 4.5kgates JTAG
Good Performance (svt lib) – peak MOPS = 8x MIPS (=MHz)
– >200 MHz WCCOM @ 1.2 V 130 nm CMOS

– >339 MHz WCCOM @ 1.1 V 45 nm CMOS (>2700 MOPS)
Low Power Consumption (core only)
– 80 μw/MHz @ 1.2 V in 130 nm CMOS
*Numbers based on svt digital CMOS libraries, comparable with TSMC. Synthesis optimized for power consumption.
Results subject to change and depend on used technology, library selection and synthesis settings
© NXP B.V. 2010

157
CoolFlux BSP – Cool Well Balanced Results*
Small core:
– 65kgates + 4.5kgates JTAG
Good Performance (svt lib) – peak MOPS = 8x MIPS (=MHz)

– >310 MHz WCCOM @ 1.1 V 45 nm CMOS (>6200 MOPS)
Low Power Consumption (core only)
*Numbers based on svt digital CMOS libraries, comparable with TSMC. Synthesis optimized for power consumption.
Results subject to change and depend on used technology, library selection and synthesis settings
© NXP B.V. 2010

158
Software development environment
(Target Compiler Technologies tool suite, distributed by NXP)
CoolFlux DSP & BSP ISA designed

together with compiler for best compiler
performance, starting from existing
compiler
– Highly efficient ANSI-C compiler:
compact, cycle efficient code,
exploiting instruction level parallelism
– No extra assembly programming
needed
– C-compiler friendly cores
Cycle-true, bit-accurate instruction set
simulator
– Source level graphic debugging
– Extensive profiling information
Complete tool suite available
– Assembler, compiler, linker, simulator
and debugger
© NXP B.V. 2010

159
Development/Demo boards
FPGA-based Board with Audio interfacing
Boards with demo chips
© NXP B.V. 2010

160
Large (and growing) Appl. Software Lib
Available : CODECS Available: RADIO
MP3 CODEC FM demodulation
WMA9 Decoder Stereo Decoding
AM demodulation
AAC LC Decoder with Dynamic Range Compression
RDS demodulation
AAC-LC Encoder with Long Windows, MS Stereo, TNS enabled
Available : OTHER
HE-AAC Vs. 1 & 2 CODEC
Bluetooth Audio Upper Stack
IMA ADPCM CODEC
Mathematical library
AMR NB CODEC
JPEG decoder
AMR WB CODEC
USB Audio Device Class
Wideband Speech CODEC G.722
Soon Available:
High quality low bit rate voice decode and encode (<10k-bps) LifeVibes Voice Engine (AEC, Noise reduction)
SBC CODEC for Bluetooth Audio Dolby Mobile
OGG Vorbis decoder Future Roadmap:
BSAC decoder G711 Voice CODEC
AC3 CODEC (5.1-Stereo) DTMF Touch Tone
Available : SOUND PROCESSING MPEG Surround
Graphic equalizer More Multi Channel Audio CODEC's
Spectrum analyzer VOIP Stack
RealAudio decoder
Dynamic Bass Boost
WMA9 Encoder
Surround Sound
WMA DRM 10
Noise reduction for voice rec.
Lossless Audio Codec
Time Scaling var. speed/keep tone for voice
Text to Speech (TTS)
MIDI playback
Sample Rate Converter
More available on customer request , future roadmap subject to customer driven
Up/Downsampling filters (first stages) for sigma delta convertors changes
© NXP B.V. 2010

161
CoolFlux BSP software libraries
12-bit complex mathlib Communication library

– FIR – Viterbi decoding
– Radix-2 FFT/IFFT • R=1/2, 1/3
– Radix-4 FFT/IFFT • Puncturing/depuncturing
– Vector functions (add, sub, mul, etc.) – Mapper/demapper
• BPSK, QPSK, 8PSK
– Complex/polar conversion • DBPSK, DQPSK, D8PSK
• 16QAM
12-bit SIMD mathlib • 64QAM
– FIR – GFSK
– Vector functions – Pseudo-random generator
– IDCT • Prbs11
• Prbs15
24-bit fixed point mathlib – FEC
– FIR • Reed-Solomon encoder/decoder
– IIR biquad • CRC
– Vector operations – OFDM Channel tracking
– Complex FFT/IFFT • Estimator
• Corrector
– Real FFT/IFFT
– – Synchronizer
Quantizers • Autocorrelation
• Linear
• ADPCM
– Frequency offset compensation
– IMDCT – Time/Interleaver/Deinterleaver
– sqrt – OFDM
– ln
© NXP B.V. 2010

162
Summary
The CoolFlux DSP & BSP are ultra low power programmable core optimized
for audio & software defined base band applications
– Well-balancing power, area and performance
– C-compiler friendly
– Robust market proven IP, over 6 years in business now without any HW bug had
to be corrected
– Extensive Application Software Library available
– Lowest Total Cost of Ownership (TCO): small area and software costs
World wide adoption by Tier 1 Semiconductor companies and OEMs
We offer partnership providing world leading expertise in:
– Ultra low power systems design
– Digital audio algorithms and acoustics & Modem development
– DSP SW maintenance
– IP design in support
THANK YOU, any questions ?
© NXP B.V. 2010

163
Rest in the comfort and security of
knowing you have Selected the
Optimum Memory IPs
Farzad Zarrinfar
Novelics Corp.
Farzad.zarrinfar@Novelics.com
IPextreme Constellations Conference - Silicon Valley 2010
March 31th , 2010, Santa Clara, Ca

Applications Driving Embedded Memory
Usage
High-Density High-Performance
High-Reliability Wide Memory Buses
MTP, OTP, Flash LCD & Other Display
Automotive Applications
High-Performance
CAM, Cache, SRAM
, e tc.
Networking
i ng ty O Ms
ir si , R
Requ h-Den MTPs
s ,
a tion & Hig OTPs
pplic wer, hes,
dg e A w-Po , Flas
ng-E e, Lo AMs
di nc ,C
Lea forma aches
h - per Ms, C
Hig , DRA
High-Performance
Ms
Low-Power & High-Density
SRA SRAM, DRAM, Flash
ded Mobile
bed
Em
High-Performance
Low-Power High-Performance
High-Density DRAM & Cache
DRAM, SRAM, Cache, OTP Office Automation
Multimedia Applications
©2008 Novelics Proprietary & Confidential
SoC Embedded Memory Usage on typical
SoC
100
90
80
Area Memory
70
Percent 60 Area Reused
of 50 Logic
Area 40 Area New

Logic
30
20
10 Source: Semico Research Corp.
0 – ASIC IP report; 2007
1999 2000 2005 2008 2011 2014 2017
Year
Increasing amount of on-chip memory

Market Demand for Memory IPs
Reliability
Power
Best
Speed
Solution
Density
Cost
Optimized Memories – Automatically

Generated!
Full nodes: 180nm, 130nm, 90nm, 65nm,
40nm
Half nodes: 160nm, 152nm, 110nm, 55nm
©2008 Novelics Proprietary & Confidential 167
Critical Factors in Selecting Mem. IPs
• Architectural Factors
• Implementation Factors
• Business Related Factors

Architectural Factors

Embedded Memory Usage on typical SoC
coolSRAM-6T coolSRAM-6T Configurable coolSRAM-1T
16 KB-I 8 KB-D Wide data buses TFT/STN Video
NTSC/PAL
4-way 4way LCD Encoder DAC
Controller
POR 2D Graphics
3D Graphics Processor SDIO
Digital
CPU Host
Signal Processor
Processor IP (Layering Engine) Controller
PLLs
•AHB
Program
2D/3D Sound
Arbiter/ 802.11 n DMA NAND Flash
Memory Processor&
AHB to APB BB& RF
&CoolROM Controller Controller
Bridge* Audio Codec
& coolREG
•APB
PCI USB
•UART TIMER* Key I •F SPI PMU RTC
Cont. Cont.
•Separate power island
•WAKEUP •Signal
MemQuestTM : Memory Compiler

Architectural Analysis & Implementation
Area/Power/Speed
Trade-offs Exploration 1
.pdf
.lib
MemQuestTM 2
.lef Front-End View
Compiler
.v
.mbist
.cir Back-End View 3
Compiler
.gds
Novelics Memory Engine &
Optimizer

• Selection Tradeoffs
 Area, Speed, Dynamic Power, Leakage, Data Retention,
Custom /std PVT, Block-by-block leakage control
• Selection of SRAM/ROM Bitcell Alternatives
• Memory Repair

MemQuest / Instance Specification Page

04/04/10
Memory Compiler for Architectural Analysis

04/04/10
coolSRAM-6T vs competitor in TSMC-65LP
Memory cut Competitor IP Type Competitor vs Novelics
depth width Size (bits) Area Tac (ns) Pwr (uA/Mhz)
64 8 512 SP 139% 188% 121%
32 64 2048 SP 176% 213% 219%
128 32 4096 SP 142% 169% 194%
512 32 16384 SP 109% 136% 178%
1024 32 32768 SP 108% 118% 207%
2048 16 32768 SP 106% 118% 201%
576 64 36864 SP 108% 132% 205%
1408 32 45056 High Speed 105% 125% 197%
2048 32 65536 SP 107% 111% 332%
1024 64 65536 SP 104% 119% 221%
4096 64 262144 SP 99% 129% 265%

04/04/10
Novelics is the Innovation Leader
• coolSRAM-6TTM :
• Lowest-power, highest-speed AND highest-density
• coolSRAM-1TTM :
• Only 1T SRAM in portable bulk CMOS process
• coolROMTM :
• Densest single layer programmable ROM
• coolREGTM :
• Highest-speed, multi-ports

• Selection of SRAM/ROM Bitcells Alternatives
 SRAM:1T, 6T, 8T
 1T Alternatives : Stack Poly, Trench Well, MIM,
Bulk CMOS (No additional masks)
 ROM Alternatives: Metal/Via/Diffusion Programmable
 Single & Dual VDD, Single & multi-VT
• Memory Repair

Typical Six-Transistor SRAM Cell

Typical One-Transistor SRAM Cell
Typical Single-Transistor/Single-Capacitor Dynamic Memory Storage Cell

Memory Density Scaling – Bulk
CMOS
Density (Mbit / mm2)
coolSRAM-1T
coolSRAM-6T
Technology Node (nm)

• Selection of SRAM/ROM Bitcell Alternatives
• Memory Repair
 (1C, 2C, 2C2R, ..Optimum Tradeoff?)

Implementation Factors

• Silicon Characteristics vs Simulation

 Commercial, Medical, Military/ Aerospace
• Memory Compiler Deliverables
• Datasheet Components
• Testability/BIST/Reliability/ Routability/Margin
Control

CMOS
• Measured cell retention time

• For a chip containing 4 Mb, the yield is > 95% without using redundancy or ECC
Silicon (ms)
Simulated (ms)
Cell Retention Time (mS)
Temperature OC


Control


 Datasheet
 Verilog model with SDF annotation support model
 Synopsys .LIB model (based on Spice characterization data)
 LEF, .NET files
 GDSII
 Documentations
o Application note & integration guide
o Versions for design rules, command files, spice models & bitcells
• Testability/BIST/Reliability/ Routability/Margin Control


Control

Compiler Generated Data Sheet -1
Sheet

Datasheet Components
Geometry Dependent
• Target Process, Top level IP diagram, external pin definition,

Timing diagram for IP functionality/ operation, AC/DC
Specifications
• Power Consumption
Min Nominal Max Unit
Active Power
a b c uW/MHz
Read Power
d e f uW/MHz
Write Power
g h i uW/MHz
Idle Power
j k l uW/MHz
Min Nominal Max Unit

Leakage Current
(ACTIVE) - n p uA
Leakage Current
(Sleep) - q r uA
* Write Power is defined as Writing: 50% 1, 50% 0

* Read power is defined as Reading: 50% 1, 50% 0


 Commercial, Medical, Military/ Aerospace
Control

Multicore SoCs :
Many SRAMs, ROMs, OTPs, Register Files, and CAMs
Instruction Cache L1 Instruction Cache L1
Register
Files
Data Cache L1 Data Cache L1 CPU
CPU
CAM CAM
Glue On-Chip ROM
Instruction Cache L2
Logic BUS Controller
OTP
Register & USB
Register Data Cache L2 Files Arbitration Logic
Files Register
Video Files
GPS ROM
GPU Memory LCD
DSP + RF SRAM (SRAM) Driver
&
ROM Register SRAM
DSP Interface
Files
Audio OTP
SRAM
Glue Logic SRAM ROM
Register
Glue Logic
Files
ROM 802.11n
Register
SRAM ROM Bluetooth DSP

Files
I/O DSP +
SRAM + RF
Data Encryption Engine
RF

Multicore SoCs :
Many SRAMs, ROMs, OTPs, Register Files, and CAMs
Instruction Cache L1 Instruction Cache L1
Register
Files
Data Cache L1 Data Cache L1 CPU
CPU
CAM CAM
Glue On-Chip ROM
Instruction Cache L2
Logic BUS Controller
OTP
Register & USB
Register Data Cache L2 Files Arbitration Logic
Files Register
Video Files
GPS ROM
GPU Memory LCD
DSP + RF SRAM (SRAM) Driver
&
ROM Register SRAM
DSP Interface
Files
Audio OTP
SRAM
Glue Logic SRAM ROM
Register
Glue Logic
Files
ROM 802.11n
Register
SRAM ROM Bluetooth DSP

Files
I/O DSP +
SRAM + RF
Data Encryption Engine
RF

Business Related Factors

• Flexible Business Model & Global Support

• Multiple Memory IPs in Single SOC
• Full Node vs Half Node Support

Flexible Licensing Business Model
• Full Use of Compiler Licensing

 Individual or combined memory engines
 Per-project or multi-year (Enterprise)
• Instance Based Licensing
 Per-project or multi-year (Enterprise)
• Flexible Royalty
• Global Sales & Technical Support


 Single Business Proposal
• Full Node vs Half Node Support


• Full Node vs Half Node Support (New Bitcell)
 Availability of IPs to meet schedule
 Availability of technology files
 Availability of Yield & Characterization data
 Optimum Wafer Price
 Viable Fab Capacity
Full nodes: 180nm,
40nm130nm, 90nm, 65nm,
Half nodes: 160nm, 152nm, 110nm, 55nm

Summary
• Successful Execution in 3 Aspects of Design

• Selecting the correct memory & Advanced Compiler
for SOC
 Maximized system performance
 Minimized system power consumption & leakage
 Minimized system manufacturing cost
• Selecting the right memory IP and the right
architecture will help you differentiate your products

Thank You!
www.Novelics.com

Posedge Inc.
The Role of Sub-System IP In Wired/Wireless Applications
Confidential
Trends in Semi Industry
• Chip companies moved from providing point
solutions to SoCs supporting multiple
features/markets
• In the last decade how the chips have evolved?

– Pure Hardware providers, Software done by the
customers (system houses)
– Today the chip providers provide complete solutions
Confidential 202
Trends in Chip Industry
PCIe
SYS
HOST
Class
BM
ACCL
Analog
PHY
QoS
nPHY
Confidential 203
Trends in IP Industry
• Started with providing point solutions
(standard interfaces, processor, etc.)
– UART /EMAC/DDR IP
lobal IP
arket in B$
Confidential 204
Trends in Sub-System IP Industry
• Growing need for IP Providers to scale up and
provide complete subsystem solutions
(Networking, Security, Graphics)
• IP providers need to understand from the system

perspective to be able to provide high value add
Confidential 205
Trends in IP Industry
Global IP Market in M$
Years – 2006 - 2012
Confidential 206
Trends in Sub-System IP
• IP provides high levels of differentiation
– End Products to various markets / segments
• IP influences the way the end system operates
– Internal Memory / DDR BW
• Performance is key
– At System Level. IP Level is of less significance.
• Significant interaction with System Software
– Need for IP players to scale up and provide much more
than just the RTL
Confidential 207
Trends in Sub-System IP Industry
• Smaller Silicon Geometries and FPGA
technologies demand more functionality and
completeness
• Early and very close interaction with the Customer
• RTL, Firmware, Software, Reference platforms
• Working w/ Customer’s Customer for specs
• Interoperating End-to-End IP
• Software API and Architectural Tools
Confidential 208
Challenges in Specialized IP
• IP as a Design Service
• Maintenance
– Configurability
– Options / Trade-Offs at Evaluation Stage
• System Perspective
– Porting to Processors
– System Level Interoperability / Standards work
• IP Product Cycles are large
– Like what ASICs used to be.
• Differentiation to various Customers
Confidential 209
Case 1: Switching / Routing
• Multi-Gigabit Switching / Routing
• Applications – STB, Wireless, Residential G/W
• Best Area/Power – (4) + 3sqmm/Gbps!!!
• 32K Table Entries / Sessions
• QoS and Traffic Management
• Software / Firmware / Hardware IP
FPGA Platform IP Core in ASIC

Confidential 210
DHCP DHCP IGMP SSH
SIGNALLING
SNMP HTTP RIP SFTP
CUSTOM
APPS TELNET FTP SNTP PING
CUSTOM APPLICATIONS UN-MODIFIED STACK

FUNCTIONS (APPS)
UDP TCP ICMP
DRIVERS IPV4 IPV6 FLOW

SETUP
HOST FUNCTIONS
IPV6/4 RTNG NAT FIREWALL STATS
L2 BDG PPPoE VLAN POLICING
CLASSIFIER (PE) FUNCTIONS

QoS MGMT BUFF MGMT ETHERNET FLOW
CNTRL
HW LEVEL FUNCTIONS
Confidential 211
ARBITERS
ARBITERS
DATA CACHE
ETHERNET BUFFER HOST
LAN/WAN MANAGER PROCESSOR
PROGRAM
CACHE
ETHERNET LOCAL
LAN/WAN MEMORY UART, SPI, GPT,
GPIO, SYSTEM
CTRL, SERIAL
FLASH
ETHERNET
LAN/WAN USB HOST
CLASSIFIER
PARALLEL USB DEV
PROCESSING
UNIT FILTERS
QOS
PCI EXPRESS
SATA
WSP IP
Video Processor
DDR
Confidential 212
Confidential 213
• Remarks
– Complete S/W, F/W, H/W IP Solution
– Best Performance
– Architecture Analysis Tools
– System Trade-offs
Confidential 214
Case 2: MACSEC / IPSEC
• 10 Gbps short packet performance
• Tight Integration to PHYs and Switches
• Fixed and Lowest Latency
• Full solution with Flow Control and MACs
IP Core in ASIC FPGA Platform
Confidential 215
Confidential 216
• 802.1X-REV & 802.1AE

• Classification
• Beyond Crypto Engine, Standards
• Secure PHY Applications
Confidential 217
• Remarks
– Working with System Vendors
– Interoperability
– System Perspective in Classification et al.
• New Applications
Confidential 218
Posedge IP Cores
Multi-Port USB-SATA Power Line

2K FFT
Routing Engine Offload Engine Comm IC
Multi-Gigabit Hardware TCP Error Coding

LDPC
Switching Core Offload Engine FEC, Viterbi
IPSEC Security MACSEC Universal Flash SOC-GEN

Engine 802.1 AE SD3.0/MMC (Bus Gen)
AXI,AHB, APB,
Public Key, IP Compression UART, SPI, GPT,
Bridge, Master,
RAND. Number GZIP, Deflate GPDMA, I2C
Slave, Arbiters
Confidential 219
Thank You
Confidential 220
Back Up Slides...
Confidential 221
Case 3: NV Memory Interface
Reference Board
SD SD Memory NAND Flash

NAND Flash
Controller Controller
HW/SW Development Kit
Highest Performance Area Others

• SD 3.0 – 104MB/sec • Cut-Thro Buffers • ECC – BCH (up to 32 bits)
• ONFI 2.2 – 200MT/sec • Clock Stopping / Read Wait • Bad Block, Wear Level, Garbage
• Hardware ECC • Modular Approach Collection
• On-the fly ECC Correction • Simple Plug and Play Interface
• Ping-Pong Mechanism • Low Power
• Interleaving Operations • HW/SW Bundle for High
• Scatter Gather DMA Performance
Confidential 222
Case 3: NV Memory Interface
• Remarks
– Performance at SoC Level
– Software + Hardware bundled IP
Confidential 223
TCP Load Engines
FPGA Platform
• Multi-Gigabit TCP Offload

• Best Area/Power/Latency!!!
– < 10 us one way
– 150K gates
• Fully Future Proof with Firmware.
• 4K-64K Sessions
IP Core in ASIC • Clean S/W Hand-offs
Confidential 224
Compression Engines
• Wireless Base Stations
• Storage Switches (Live)
• Back-Up Servers
Memory
FPGA Platform
Huffman Encoder
• Multi-Gigabit Compression Engine
DATA IN for Distance
COMP
10 Gbps Data
•
LZ 77 DATA OUT
Parser
Engine
Find
Huffman Encoder
Pack
Best Area/Power/Latency!!!
Tree , Literals /
length
– < 0.5 us one way
COMP
INP DATA LZ77
Huffman
Table
Data
Inflate
10 Gbps
DATA OUT – 120K gates
UPack Decode and
Engine
Decoder
• Novel LZ77 Architecture

AHB /AXI
Host Debug Statistics Memory • IPCOMP
Confidential 225
Thank You
Confidential 226
Technical Panel Discussion
Slide 227
Confidential Slide 227

Constellations 2010 Silicon Valley - Complete Slide Set

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Constellations 2010 Silicon Valley - Complete Slide Set

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Constellations Conference

Silicon Valley 2010

Legend Soft IP Hard IP Software Other

9:15am Welcome & Introductions Warren Savage

9:25am Keynote Presentation Jim Hogan

9:40am Increasing ESD Challenges Stephen Fairbanks

10:00am Integrating high performance, ultra-low power Serge Maginot

10:40am Panel: IP Business Models

© IPextreme, Inc. Confidential Information. Slide 3

12:15pm Leveraging Your On-chip Networks and Maximizing Jack Browne

1:15pm Bringing HD video to multimedia applications Philip Han

1:35pm Afternoon Break & Refreshments

2:35pm The role of Networking IP in Wired/Wireless Surya Hotha

© IPextreme, Inc. Confidential Information. Slide 4

2:55pm Panel: Technical Considerations

3:55pm Luck Draw – Apple iPad

4:10pm Closing Statement Warren Savage

© IPextreme, Inc. Confidential Information. Slide 5

• Costs are escalating 15.0

beyond the reach of many 10.0

digit growth HW Growth Rate (%)

HW Growth (%) SW Growth (%)

• Shed the need for ongoing investment in ubiquitous design

Digital Rights Mgmt

• Architectural Intent must solidify the tool chain

• Architectural Intent must be transparent

• Huge mistake to ignore US and Japan Synopsys Cadence Mentor

About Certus Semiconductor, LLC.

Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential 24

 A few realities about ESD

 Its hard to qualify the ESD impact

Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential

 Increasing Challenges about ESD

NMOS Failure Trends: Jedec

Copyright © CERTUS Semic., LLC, 2010 proprietary & confidential 26

Increasing Challenges about ESD

 Traditional IP block integration had all the ESD

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 Internal Failures are

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As products increase in complexity and technologies

March 31st , 2010

• Offer powerful asynchronous core IPs supported

Contactless and other Ultra-low power Mobile consumer Automotive Aerospace

Ultra-low power Works at variable

Tiempo asynchronous design technology offers

• Breaking today’s barriers: on a

• Breaking tomorrow’s barriers

• Ex: 0.6V on CMOS 130 nm GP

• Technology for the design of asynchronous and delay insensitive

Synchronous Data Reg Logic Reg Logic Reg

• Power-efficient instruction set

• Instruction set can be easily customized

• TAM16 chip includes

• Next silicon: run in Feb 2010

• Standard ciphering & deciphering AES

• Top-level interface choice

• Top-level interface choice

• Applications: low power & high

• Mobile consumer electronics

• Lower energy consumption

Memory, debug, coprocessor

• Lower current peaks (/15)

Place & Route STA Asynchronous-