Microprocessors:

General-purpose microprocessor

CPU for Computers

No RAM, ROM, I/O on CPU chip itself

Example Intels x86, Motorolas 680x0

CPU
GeneralPurpose
Microprocessor

Many chips on mothers board

Data Bus

RAM

ROM

I/O
Port

Address Bus
General-Purpose Microprocessor System

Timer

Serial
COM
Port

Microcontroller :
A smaller

computer
On-chip RAM, ROM, I/O ports...
Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU
I/O
Port

RAM ROM
Serial
Timer COM
Port

A single chip
Microcontroller

Microprocessor

Microcontroller

Microprocessor Contains ALU ,

General Purpose Registers, SP,
PC Clock Timing Circuit and
Interrupt control Circuit

Microcontroller Contain the

Circuitry of P and in Addition it
has built in ROM, RAM , I/O
Ports, Timers and Counters

It has one or two Bit handling

Instructions

It has many Bit handling

Instructions

The Instruction set of

microprocessor is complex with
large number of instructions.

The instruction set of a

Microcontroller is very simple
with less number of
instructions.

Less Number of pins are

Multifunctional

More Number of pins are

Multifunctional

Access Time for Memory & I/O

devices are more

Less Access time for Built in

Memory and I/O Devices

It has Single memory map for

data and Code.

Separate Memory Map for data

and Code

Microprocessors are most

commonly used as the CPU in
microcomputer systems

Microcontrollers are used in

small, minimum component
designs performing controloriented embedded

Von Neumann architecture

Processor

Having Architecture with Single Bus

and Single Memory to hold both instructions and
data is known as Von Neumann Architecture .

In

a computer with a von Neumann architecture

(and no cache), the CPU can be either reading an
instruction or reading/writing data from/to the
memory.
Both cannot occur at the same time since the
instructions and data use the same bus system.
.

This

Architecture will make the Program

Execution slow.

The von Neumann model

CPU

So where is the
Input/Output?
here

Input

Output

Buses

Harvard architecture
The

Harvard Architecture use Physically

Separate memory for instruction and Data,
and have dedicated buses for each of them.

Instruction

and Data can be fetched

Simultaneously.

Different

Program and Data bus width are

Possible , allowing program and data Memory
to be better optimized to the Architectural
Requirement.

Harvard architecture

address
data memory

data
address

program memory

data

PC
CPU

Von Neumann

Harvard

Processor Having Architecture

with Single Bus and Single
Memory to hold both
instructions and data is known
as Von Neumann Architecture

The Harvard Architecture use

Physically Separate memory for
instruction and Data, and have
dedicated buses for each of
them

In a computer with a von

Neumann architecture (and no
cache), the CPU can be either
reading an instruction or
reading/writing data from/to the
memory

In a computer using the Harvard

architecture, the CPU can read
both an instruction and perform
a data memory access at the
same time, even without a
cache.

In Von Neumann Architecture

the Program Execution is Slow

A Harvard architecture
computer can thus be faster

CISC Processor

RISC Processor

Complex Instruction Set

Computer

Reduced Instruction Set

Computer

Large Number of Complex

Instructions

Small Number Of Instructions

Instructions are of Variable

number of bytes

Instructions are of Fixed number

of Bytes

When an MCU Supports many

addressing modes for arithmetic
and logical instructions and for
M/Y access and data transfer
instructions the MCU is said to
be CISC architecture

When an MCU has an instruction

set that Supports one or two
addressing modes for arithmetic
and logical instructions and few
M/Y access and data transfer
instructions the MCU is said to
be CISC architecture

Instruction take variable amount Instruction take fixed amount of

of time for execution
time for Execution
Small Code size and Emphasis
on Hardwire design

Large Code Size and Emphasis

on Software Design

Small Amount of Cache and

very few Registers

Large Cache and Large Number

Of Registers

Criteria for Choosing a Micro- Controller

Criteria for Choosing a Micro Controller

Over View Of 8051 Family

Various 8051 Micro Controllers

Features of 8051 Micro Controllers

SALIENT FEATURES : The salient features of 8051

Microcontroller are

I. 4 KB on chip program memory (ROM or EPROM)).

ii. 128 bytes on chip data memory(RAM).

iii. 8-bit data bus

iv. 16-bit address bus

v. 32 general purpose registers each of 8 bits

vi. Two -16 bit timers T0 and T1

vii. Five Interrupts (3 internal and 2 external).

ix. Four Parallel ports each of 8-bits (PORT0, PORT1,PORT2,PORT3)

with a total of 32 I/O lines.

x. One 16-bit program counter and One 16-bit DPTR ( data pointer)

xi. One 8-bit stack pointer

xii. One Microsecond instruction cycle with 12 MHz Crystal.

xiii. One full duplex serial communication port.

89C51 Architectural Block Diagram

89C51 Architectural Block Diagram

A and B Registers : The A and B registers are special function

registers which hold the results of many arithmetic and logical
operations of 8051.The A register is also called the Accumulator
and as its name suggests, is used as a general register to
accumulate the results of a large number of instructions. The B
register is mainly used for multiplication and division operations
along with A register.
Program Counter(PC) : 8051 has a 16-bit program counter .The
program counter always points to the address of the next
instruction to be executed.
Stack Pointer Register (SP) : It is an 8-bit register which stores
the address of the stack top. i.e the Stack Pointer is used to
indicate where the next value to be removed from the stack
should be taken from. When a value is pushed onto the stack, the
8051 first increments the value of SP and then stores the value at
the resulting memory location. Similarly when a value is popped off
the stack, the 8051 returns the value from the memory location
indicated by SP, and then decrements the value of SP

Data Pointer Register(DPTR) : It is a 16-bit register which is

the only user-accessible. DPTR, as the name suggests, is used
to point to data. It is used by a number of commands which allow
the 8051 to access external memory. When the 8051 accesses
external memory it will access external memory at the address
indicated by DPTR

Program Status Register (PSW) : The 8051 has a 8-bit PSW

register which is also known as Flag register. In the 8-bit register
only 6-bits are used by 8051.The two unused bits are user
definable bits.In the 6-bits four of them are conditional flags
.They are Carry CY, Auxiliary Carry-AC, Parity-P,and Overflow-OV
.These flag bits indicate some conditions that resulted after an
instruction was executed.

Internal RAM OF 8051 :

The 128 bytes of internal RAM is organized as below.

(I) Four register banks (Bank0,Bank1, Bank2 and Bank3)

each of 8-bits (total 32 bytes). The default bank register
is Bank0. The remaining Banks are selected with the help of
RS0 and RS1 bits of PSW Register.

(ii) 16 bytes of bit addressable area

(iii) 80 bytes of general purpose area (Scratch pad memory).

This area is also utilized by the microcontroller as a storage
area for the operating stack.

In Addition to the 128 Bytes of Internal RAM , there are

Special Function Registers , that are used for Different
applications.

and

23

SPECIAL FUNCTION REGISTERS (SFRs) : In 8051 microcontroller

there certain registers which uses the RAM addresses from 80h to FFH
and they are meant for certain specific operations .These registers are
called Special function registers (SFRs).Some of these registers are bit
addressable also.

Internal ROM (On chip ROM):

The 8051 microcontroller has 4kB of on chip ROM but it can
be extended up to 64kB.This ROM is also called program
memory or code memory. The external ROM is accessed when
the EA(active low) pin is connected to ground or the contents of
program counter exceeds 0FFFH.When the Internal ROM address
is exceeded the 8051 automatically fetches the code bytes from
the external program memory

I/O PORTS
(1)

One of the major features of a microcontroller is the versatility built into

the I/O circuits that connect the microcontroller to the outside world .

(2) One of the most useful features of the 8051 is four bidirectional I/O
ports.
(3) Each port has an 8-bit latch in the SFR space as mentioned earlier.
(4)To reduce the overall package pin count, the 8051 employs multiple
functions for each port.
(5) Each port also has an output drive and an input buffer.
(6) These ports can be used to general purpose I/O, as an address and data
lines.
(7) The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins

I/O PORTS

27

PORT 0
(1) Port 0 is 8-bitbidirectional I/O port.
Port 0 is also the multiplexed low-order address and data bus during
accesses to external program and data memory.
(2) If external memory is used, these port pins are used for the lower
address byte address/data (AD0-AD7), otherwise all bits of the port are
either input or output.
(3) ALE indicates whether P0 has address or data. When ALE = 0, it
provides data D0-D7, and when ALE =1 it provides address and data
with the help of a 74LS373 latch
(4) Unlike other ports, Port 0 is not provided with pull-up resistors
internally ,so for PORT0 pull-up resistors of nearly 10k are to be
connected externally as shown in the fig

28

PORT 1
(1)

Port 1 occupies a total of 8 pins (pins 1 through 8). It has no dual

application and acts only as input or output port.

(2) Port 1 have no dual functions.

(3) Upon reset, Port 1 is configured as an output port. To configure it as
an input port , port bits must be set i.e a high bit must be sent to
all the port pins

PORT 2
(1)Port 2 is an 8-bit bidirectional I/O port.
(2)Port 2 emits the high-order address byte (A8-A15) during fetches from
external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). While P0 provides
the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of
the address.

29

PORT 2
(1)Port 2 is an 8-bit bidirectional I/O port.
(2)Port 2 emits the high-order address byte (A8-A15) during fetches from
external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). While P0 provides
the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of
the address.

PORT 3
(1)

Port 3 is an 8-bit bi-directional I/0 port.

(2)

Port 3 has Alternative Functions

RXD (P3.0): Serial input port (RXD)

TXD (P3.1): Serial output port (TXD)

INT0 (P3.2): External interrupt (INT0)

INT1 (P3.3): External interrupt (INT1)

T0 T0 (P3.4): Timer 0 external input (T0)

T1 (P3.5): Timer 1 external input (T1)

WR (P3.6): External data memory write strobe (WR)

RD (P3.7): External data memory read strobe (RD)

30

Ports

31

Hardware Structure of I/O Pin

Each pin of I/O ports

Internal CPU bus communicate with CPU
A D latch store the value of this pin
D latch is controlled by Write to latch
Write to latch 1 write data into the D latch
2 Tri-state buffer
TB1: controlled by Read pin
Read pin 1 really read the data present at the pin
TB2: controlled by Read latch
Read latch 1 read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close

D Latch:

A Pin of Port 1
Read latch

TB2

Vcc
Load(L1)

Internal CPU
bus

Write to latch

Clk

P1.X
pin

P1.X
Q

M1

TB1
Read pin

P0.x

PORT 1 as Input port

Reading High at Input Pin

Read latch
1.

TB2

write a 1 to the pin MOV

P1,#0FFH
Internal CPU bus

2. MOV A,P1

Vcc

external pin=High
Load(L1)

P1.X
Write to latch

Clk

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1

M1

P1.X pin