Microprocessor Systems

I/O System Design

Introduction
I/O devices serve two main purposes
To communicate with outside world
To store data

I/O controller acts as an interface between the systems bus

and I/O device
Relieves the processor of low-level details
Takes care of electrical interface

I/O controllers have three types of registers

Data
Command
Status
2

Introduction (contd)

Introduction (contd)
To communicate with an I/O device, we need
Access to various registers (data, status,)
This access depends on I/O mapping
Two basic ways
Memory-mapped I/O
Isolated I/O

A protocol to communicate (to send data, )

Three types
Programmed I/O
Interrupt-driven I/O
Direct memory access (DMA)

Accessing I/O Devices

I/O address mapping
Memory-mapped I/O
Reading and writing are similar to memory read/write
Uses same memory read and write signals
Most processors use this I/O mapping

Isolated I/O
Separate I/O address space
Separate I/O read and write signals are needed
Pentium supports isolated I/O

FFFFF

64 KB address space
Can be any combination of 8-, 16- and 32-bit I/O ports
Also supports memory-mapped I/O
FFFFF
Memory
addressing
space

00000

I/O
FFFF I/O
addressing
0000 space

Direct I/O

00000

Memory addressing
space

Memory-mapped I/O

Accessing I/O Devices (contd)

Accessing I/O ports in 80x86
Register I/O instructions
in

accumulator, port8

; direct format

Useful to access first 256 ports

in

accumulator,DX

; indirect format

DX gives the port address

8086/88 Port Addressing Space

Addressing Space

Accessing directly by instructions

IN
IN
OUT
OUT

FFFF

Accessed
through
DX

00FF
00F8

Accessed
directly by
instructions

AL,
AX,
3CH,
0A0H,

80H
6H
AL
AX

Accessing through DX
IN
AL,
IN
AX,
OUT DX,
OUT DX,

DX
DX
AL
AX

0000
7

Input Port Implementation

Data Bus

8086/88

Gating
device

Address bus

Input

Decoder
Other control
signals

The outputs of the gating device are high impedance when the processor is not
accessing the input port
When the processor is accessing the input port, the gating device transfers input
data to CPU data bus
The decoding circuit controls when the gating device has high impedance output
and when it transfers input data to data bus
8

Input Port Implementation

Circuit Implementation
Assume that the address of the input port is 9CH

A7
A6
A5
A4
A3
A2
A1
A0

Data bus

Tri-state
buffer

Input data

CE

RD IO/M

Input Port Implementation

10

Output Port Implementation

Circuit Implementation
Assume that the address of the output port is 9CH

A7
A6
A5
A4
A3
A2
A1
A0

Data bus

Latch

Output data

CLK

WR IO/M

11

Output Port Implementation

12

A Reconfigurable Port Decoder

1

A6
A5

A=B
B3
A3
B2
A2
B1
A1

A4

A0

A7

Vcc
R

B0
A=B

A2
A1

A=B
B3
A3
B2
A2
B1
A1

A0

A0

A3

B0
A=B

RD or WR
IO/M
13

An Example I/O Device

Keyboard
Keyboard controller scans and reports
Key depressions and releases

Supplies key identity as a scan code

Scan code is like a sequence number of the key
Keys scan code depends on its position on the keyboard
No relation to the ASCII value of the key

Interfaced through an 8-bit parallel I/O port

Originally supported by 8255 programmable peripheral
interface chip (PPI)

14

An Example I/O Device (contd)

8255 PPI has three 8-bit registers
Port A (PA)
Port B (PB)
Port C (PC)

These ports are mapped as follows

8255 register
PA (input port)
PB (output port)
PC (input port)
Command register

Port address
60H
61H
62H
63H
15

An Example I/O Device (contd)

Mapping of 8255 I/O ports

16

An Example I/O Device (contd)

Mapping I/O ports is similar to mapping memory
Partial mapping
Full mapping

Keyboard scan code and status can be read from

port 60H
7-bit scan code is available from
PA0 PA6

Key status is available from PA7

PA7 = 0 key depressed
PA0 = 1 key released
17

I/O Data Transfer

Data transfer involves two phases
A data transfer phase
It can be done either by
Programmed I/O
DMA

An end-notification phase
Programmed I/O
Interrupt

Three basic techniques

Programmed I/O
DMA
Interrupt-driven I/O
18

I/O Data Transfer (contd)

Programmed I/O
Done by busy-waiting
This process is called polling

Example
Reading a key from the keyboard involves
Waiting for PA7 bit to go low
Indicates that a key is pressed

Reading the key scan code

Translating it to the ASCII value
Waiting until the key is released
19

8255 Programmable Peripheral

Interface

20

8255 Programmable Peripheral Interface

21

Introduction (contd)

22

8255 PPI : Functional Diagram

23

8255 Programmable Peripheral Interface

Data bus
A0
A1
RD
WR
RESET

8088

A7
A6
A5
A4
A3
A2
IO/M

D[7:0]

PA[7:0]
PB[7:0]

Control port

PC[7:0]

CS

A1

A0

0
0
1
1

0
1
0
1

Port
PA
PB
PC
Control
24

8086/88 Port Addressing Space

Addressing Space

Accessing directly by instructions

IN
IN
OUT
OUT

FFFF

Accessed
through
DX

00FF
00F8

Accessed
directly by
instructions

AL,
AX,
3CH,
0A0H,

80H
6H
AL
AX

Accessing through DX
IN
AL,
IN
AX,
OUT DX,
OUT DX,

DX
DX
AL
AX

0000
25

Programming 8255
8255 has three operation modes: mode 0, mode 1, and mode 2

26

Programming 8255
Mode 0:
Ports A, B, and C can be individually programmed as input or output ports
Port C is divided into two 4-bit ports which are independent from each other

Mode 1:
Ports A and B are programmed as input or output ports
Port C is used for handshaking

PC4
PC5
PC3

8255

PA[7:0]
STBA
IBFA
INTRA
PB[7:0]

PC2
PC1
PC0
PC6, 7

STBB
IBFB
INTRB

PC7
PC6
PC3

8255

PA[7:0]
OBFA
ACKA
INTRA
PB[7:0]

PC2
PC1
PC0
PC4, 5

OBFB
ACKB
INTRB
27

Input Port Implementation

Circuit Implementation
Assume that the address of the input port is 9CH

A7
A6
A5
A4
A3
A2
A1
A0

Data bus

Tri-state
buffer

Input data

CE

RD IO/M

28

Programming 8255
Mode 0:
Ports A, B, and C can be individually programmed as input or output ports
Port C is divided into two 4-bit ports which are independent from each other

Mode 1:
Ports A and B are programmed as input or output ports
Port C is used for handshaking

PC4
PC5
PC3

8255

PA[7:0]
STBA
IBFA
INTRA
PB[7:0]

PC2
PC1
PC0
PC6, 7

STBB
IBFB
INTRB

PC7
PC6
PC3

8255

PA[7:0]
OBFA
ACKA
INTRA
PB[7:0]

PC2
PC1
PC0
PC4, 5

OBFB
ACKB
INTRB
29

Programming 8255
Mode 2:
Port A is programmed to be bi-directional
Port C is for handshaking
Port B can be either input or output in mode 0 or mode 1
PA[7:0]

8255

PC7
PC6
PC4
PC5
PC3
PC0
PC0
PC0

OBFA
ACKA
STBA
IBFA
INTRA
In
In
In
PB[7:0]

1.
2.

Out
Out
Out

STBB
IBFB
INTRB

OBFB
ACKB
INTRB

Mode 1
Mode 0
Can you design a decoder for an 8255 chip such that its base address is 40H?
Write the instructions that set 8255 into mode 0, port A as input, port B as output,
PC0-PC3 as input, PC4-PC7 as output ?
32

Timing diagram is a combination of the Mode 1 Strobed Input

and Mode 1 Strobed Output Timing diagrams.

Example: Mode 1 Input

keyboard

8255
PA0

BIT5 EQU
PORTC
PORTA

20H
EQU
EQU

READ
Read:

PROC NEAR

IN AL, PORTC
TEST AL, BIT5
JZ Read
IN AL, PORTA

READ

22H
20H

PA7

STB
PC4

DAV

; read portc
;test IBF
;if IBF=0
;Read Data

ENDP
34

Example: Mode 1 output

Printer

8255
PB0
PB7

ACK
PC2

ACK

PC4

DS

Data Strobe : to tell

the printer to latch the
incoming data.
Generated Externally

35

Example: Mode 1 output

BIT1 EQU
PORTC
PORTB
CMD EQU
PRINT PROC

2
EQU 62H
EQU 61H
63H
NEAR

; check printer ready?

IN AL, PORTC ;get OBF
TEST AL, BIT1 ;test OBF
JZ PRINT ;if OBF=0 buffer is
full

;send character to printer

MOV AL, AH ;get data
OUT PORTB, AL ;print data
; send data strobe to printer
MOV AL, 8 ;clear DS
OUT CMD, AL
MOV AL, 9 ;clear DS
OUT CMD, AL
;rising the data at the positive
edge of DS
RET

PRINT ENDP
36

Keyboard example

37

Keyboard example

38

Bouncing Problem

39

Bouncing

40

Software Solution

41

De-bouncing Circuitry
Two asynchronous flip-flop solutions are given below

The basic idea is that these flip-flops store the values even if the D/D
nodes both float
42

Another Solution

43

External Interface
Two ways of interfacing I/O devices
Serial
Cheaper
Slower

Parallel
Faster
Limited to small
distances

44

External Interface
Two basic modes of data transmission

45

External Interface
Serial transmission
Asynchronous
Each byte is encoded for transmission
Start and stop bits

No need for sender and receiver synchronization

Synchronous
Sender and receiver must synchronize
Block of data can be sent
More efficient
Less overhead than asynchronous transmission

Expensive
46

External Interface

47

External Interface
Asynchronous transmission

48

Data Communications

Data Communications: MODEM

Modems
can be internal, in which they plug into a slot
inside a computer
external, in which they are separate from the
computer and require a serial cable and their own
power supply.

Internal modems do not require a serial cable but

instead require an IRQ assigned.

Partially internal modems in laptops, PC Cards, PC

Card Hosts and PC Card Software PCMCI

MODEMS

MODEMS

External Interface
EIA (Electronics Industries
Association) -232 serial interface
Low-speed serial transmission
Adopted by Electronics Industry
Association (EIA)
Popularly known by its predecessor
RS-232

It uses a 9-pin connector DB-9

Uses 8 signals

Typically used to connect a modem to

a computer

53

External Interface
Transmission protocol uses three phases
Connection setup
Computer A asserts DTE (Data Terminal Equipment)
Ready
Transmits phone# via Transmit Data line (pin 2)

Modem B alerts its computer via Ring Indicator (pin

9)
Computer B asserts DTE Ready (pin 4)
Modem B generates carrier and turns its DCE (Data
Communication Equipment) Ready

Modem A detects the carrier signal from modem B

Modem A alters its computer via Carrier Detect (pin 1)
Turns its DCE Ready
54

External Interface
The last two phases of Transmission
protocol
Data transmission

Done by handshaking using

Request-to-send (RTS) and clear-to-send (CTS) signals

Connection termination
Done by deactivating RTS

55

Serial Data Transfer

Asynchronous v.s. Synchronous

Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication
Synchronous transfer does not transfer extra bits. However, it requires clock signal
Frame
Asynchronous
Data transfer

data
Start
bit B0 B1 B2 B3 B4

B5 B6
Stop bits
Parity

clk
Synchronous
Data transfer

data
B0

B1

B2

B3

B4

B5

Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

56

8251 USART Interface

8251
D[7:0]

RS232

TxD

RD
WR
A0

RD
WR
C/D

CLK

CLK

RxD
TxC
RxC

A7
A6
A5
A4
A3
A2
A1
IO/M
57

8251: Functional Diagram

Functional block diagram of 8251A-USART

58

8251: Pin Description

CLK (Input terminal)
CLK signal is used to generate internal device timing

CLK signal is independent of RXC or TXC

However
Frequency of CLK must be greater than 30 times the
RXC and TXC
Synchronous mode
Asynchronous "x1" mode

Frequency of CLK must be greater than 5 times at

Asynchronous "x16" and "x64" mode
59

8251: Pin Description

C/D (Input terminal)

which receives a signal for selecting data or command words and

status words when the 8251 is accessed by the CPU
If C/D = low, data will be accessed
If C/D = high, command word or status word will be accessed

TXD (output terminal)

For transmitting serial-converted data
High level
after resetting or
when transmit is disabled

Low level
It is also possible to set the device in "break status" (low level) by a
command.
60

8251: Pin Description

TXEMPTY (Output terminal)

High level
This is an output terminal which indicates that the 8251 has
transmitted all the characters and had no data character
In "synchronous mode," the terminal is at high level,
sync characters are automatically transmitted
If the CPU writes a data character, TXEMPTY will be reset by the
leading edge of WR signal.

61

8251: Pin Description

TxC (Input terminal)
This is a clock input signal which determines the transfer
speed of transmitted data

In "synchronous mode,"
the baud rate will be the same as the frequency of TxC

In "asynchronous mode
it is possible to select the baud rate factor by mode
instruction
It can be 1, 1/16 or 1/64 the TxC
The falling edge of TxC shifts the serial data out of the
8251
62

8251: Pin Description

RxC (Input terminal)
This is a clock input signal which determines the
transfer speed of received data

In "synchronous mode,"
the baud rate will be the same as the frequency of RxC

In asynchronous mode
It is possible to select the baud rate factor by mode
instruction
It can be 1, 1/16 or 1/64 the TXC

63

8251: Pin Description

SYNDET/BD (Input or output terminal)
This is a terminal whose function changes according to
mode
In "internal synchronous mode" this terminal is at high
level, if sync characters are received and synchronized
In "external synchronous mode
"this is an input terminal
A "High" on this input forces the 8251 to start receiving data
characters

64

8251: Pin Description

SYNDET/BD (Input or output terminal)

In "asynchronous mode,"
this is an output terminal which generates "high level
output
Upon the detection of a "break" character if receiver data
contains a "low-level" space between the stop bits of two
continuous characters

The terminal will be reset, if RxD is at high level

After Reset is active, the terminal output will be at low
level

65

66

Programming 8251: Asynchronous Mode

Serial Transmit and Receive in Asynchronous
Mode

67

Programming 8251
8251 mode register: to initialize 8251, Mode word is to be sent followed
by command word
7

Number of
Stop bits
00:
01:
10:
11:

invalid
1 bit
1.5 bits
2 bits

Mode register

Baud Rate

Parity enable
0: disable
1: enable
Character length

Parity
0: odd
1: even

00:
01:
10:
11:

00: Syn. Mode

01: x1 clock
10: x16 clock
11: x64 clock

5 bits
6 bits
7 bits
8 bits

Fig. 2 Bit configuration of Asynchronous Mode

68

Programming 8251: Mode Word

Mode Instruction
Mode instruction is used for setting the function of the 8251. \
Mode instruction will be in "wait for write" at either internal reset or
external reset
writing of a control word after resetting will be recognized as a
"mode instruction."
Items set by mode instruction are as follows
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)
Number of synchronous characters (Synchronous mode)
69

Programming 8251: Mode Word: Synchronous

70

Programming 8251: Mode Word

Synchronous Mode
In the case of synchronous mode, it is necessary to write
one-or two byte sync characters
If sync characters were written, a function will be set
because the writing of sync characters constitutes part of
mode instruction

71

Programming 8251
Baud Rate factor
Ratio between the clock applied to TxC-RxC inputs and the desired
baud rate
For example
To use transmitter clock (TXC) of 19,200Hz
for transmitting data at 1200 Bd
The baud rate factor = 19,200/1200 or 16x
In synchronous data transfer,
D1- D0 = 00
Baud rate will be same as the TxC and RxC

72

Programming 8251: Command Word

8251 command register
EH

TxE:
DTR:
RxE:

IR

RTS

ER

SBRK

RxE

DTR

TxE

Command register

Transmitter enable --- 1=Enable,

0= Disable
Data terminal ready --- 1=DTR pin will be low
Receiver enable --1= Enable RxDY, 0= Disable RxDY

SBRK: Send break character -- 1= Forces TxD pin will be low

0= For normal operation
ER:
Error reset
1=Reset all error flags (PE,OE,FE)
RTS:
Request to send-- 1= RTS pin will be forced low
IR:
Internal reset -1= Returns 8251 to mode instruction
format
EH:
Enter hunt mode -- 1= Enable search for SYN character codes

73

Programming 8251: Command Word

Command
Command is used for setting the operation of the
8251
It is possible to write a command whenever
necessary after writing a mode instruction and sync
characters
Items to be set by command are as follows
Transmit Enable/Disable
Receive Enable/Disable
DTR, RTS Output of data
Resetting of error flag
Sending break characters
Internal resetting
Hunt mode (synchronous mode)

74

Programming 8251
8251 status register
DSR

SYNDET

FE

OE

PE

TxEMPTY RxRDY TxRDY

status register

TxRDY: Transmitter readyIndicates USART is ready to accept data

character or command
RxRDY: Receiver readyUSART has received a character on its RxD
and is ready to transfer to CPU
TxEMPTY: Transmitter empty
PE: Parity errorset when parity error is detected
It is reset by ER bit of command instruction
PE doesnt inhibit the operation of USART
OE: Overrun error-- when CPU doesnt read a character before the next
one becomes available
FE: framing error---when a valid stop bit is not detected at the end of
every character
SYNDET: Sync. character detected
DSR: Data set ready general purpose used to test modem condition

75

Asynchronous Transmission
Figure below shows the polarities used on EIA-232 circuits
While there are no data to send (idle), the data circuit is at a
negative voltage

76

Programming 8251:Asynchronous Mode

77

78

Programming 8251: Synchronous Transmission

79

Simple Serial I/O Procedures

Read

Write
start

start

Check RxRDY

Check TxRDY

Is it logic 1?

No

Is it logic 1?

Yes
Read data register*
end
* This clears RxRDY

No

Yes
Write data register*
end
* This clears TxRDY
80

Programming 8251
Q1. Write an 8086 assembly language procedure to transmit the contents of
register AH to the 8251 USART and out through its serial data pin, when the
TxRDY bit (bit 0 in the Control register) is set. Assume a Data and Control
address of FEH and FFH, respectively.
CONTROL
EQU FFH
DATA
EQU FEH
SEND PROC NEAR
PUSH AX
SEND1:
IN AL, CONTROL ; Is TxRDY? = 1
TEST AL, 01H ; 0000 0001
JZ SEND1
; Transmit data
MOV AL, AH
OUT DATA, AL ; Transmit a Character
POP AX
RET
SEND ENDP
81

Programming 8251
Q2. Write an 8086 assembly language procedure to test the RxRDY bit
(bit 1 in the Control register), to decide if the 8251 has received data, and
then return with the received data in register AL. Assume a Data and
Control address of C2H and C3H, respectively.
CONTROL
EQU C3H
DATA
EQU C2H
RECV PROC NEAR
PUSH AX
RECV1:
IN AL, CONTROL ; Is RxRDY? = 1
TEST AL, 02H ; 0000 0010
JZ RECV1
; Read Data
IN AL, DATA ; Receive a character
POP AX
RET

82

Errors
Parity error: Received data has wrong parity
error -- transmission bit flip due to noise.

Framing error: Start and stop bits not in their proper

places.
This usually results if the receiver is receiving data at the
incorrect baud rate.

Overrun error: Data has overrun the internal receiver

FIFO buffer.
Software is failing to read the data from the FIFO.

83

External Interface
Parallel printer interface
A simple parallel interface
Uses 25-pin DB-25
8 data signals
Latched by strobe (pin 1)

Data transfer uses simple handshaking

Uses acknowledge (CK) signal
After each byte, computer waits for ACK

5 lines for printer status

Busy, out-of-paper, online/offline, autofeed, and fault

Can be initialized with INIT

Clears the printer buffer and resets the printer
84

External Interface (contd)

85

DMA

86