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CONTENT
Soft IP vs Hard IP
Design for timing closure : Logic design
issues
Design for verification
System interconnect and on-chip
buses
Design for low power
Design for test: Manufacturing test
strategies
Soft IP vs Hard IP
Synthesis, placement, and routing then
and
Macro Interfaces
Subblock Interfaces
2. Synchronous vs.
Asynchronous Design Style
Rule The system should be synchronous
3. Clocking
SoC
Clock Planning
Rule
The system clock generation and control
4. Reset
Rule The basic reset strategy for the chip must
be documented.
Synchronous reset:
Advantage: Is easy to synthesize.
Disadvantage: Requires a free-running clock.
Asynchronous reset:
Advantage: Does not require a free-running clock.
Uses separate input on flop, so it does not affect
flop data timing.
Disadvantage: Is harder to implement.
Makes static timing analysis and cycle-based
simulation more difficult.
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