8259

Programmable Interrupt
Controller

8259 FEATURES
Standard chip which acts as an interrupt manager for a system
Depending on the size and requirements of the system ,there
can be one or more interrupt controllers .

Fig:- Basic connection between 8259 and

8086

The PIC has eight interrupt request lines IR0 to IR7 ,on which peripherals
can place their interrupt requests .

If one interrupt request alone is received on the chip, that request is

channeled to the INTR line of the processor.

The processor sends back the

PIC sends 8086 the interrupt number corresponding to the interrupt.

PIC has been programmed to send a specific type number

for a particular interrupt request.

signal.

Another activity of the chip is to resolve priorities.

If there is a possibility of more that 8 interrupt sources , more

PICs can be used

Chip has pins for cascading more of such chips ,and a

particular chip can be a master or a slave.

BLOCK DIAGRAM
Intel 8259A Programmable Interrupt Controller handles up to
eight vectored priority interrupts for the CPU.
It is cascadable for up to 64 vectored priority interrupts .
It is packaged in a 28-pin DIP.
Requires a single 5V supply.
Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real
time overhead in handling multi- level priority interrupts.

Functional block diagram

It

has

interrupt

request lines IR0 to IR7,

which are asynchronous
inputs lines.
An interrupt request is
executed by

Raising an IR input
(low

to

high),

and

holding it high until it

is

acknowledged

(Edge

Triggered

Mode),
Just by a high level on
an

IR

input

(Level

Internal Block Diagram

Pin Functions
INT:
This output goes directly to processor interrupt input and
causes the processor to send back the
as an
acknowledgement.
IRR &ISR
Interrupts at the IR input lines are handled by two
registers in cascade.

IRR (Interrupt Request Register) is used to store all the

interrupt levels which are requesting service.

ISR (In Service Register) is used to store the interrupt

levels which are being serviced.

PRIORITY RESOLVER
Determines the priorities of the bits set in the IRR.
The highest priority is selected and strobed into the
corresponding bit of the ISR(in service register) during

INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interrupt lines to be masked.
The IMR operates on the IRR.
Masking of a higher priority input will not affect the interrupt request lines of lower
priority.
CAS0-CAS2 :
Three bi-directional lines can be used to cascade several such chips to expand
the number of interrupts up to 64,in a master or slave mode .

The associated three I/O pins (CAS 0-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a slave.

This stands for Slave Program/Enable Buffer .

This is also a bidirectional pin

R/W Logic:
Decoding logic on the
and A0 determine the addresses of the registers within
the chip ,and in conjunction with the
signals registers can be read
from or written into.

INTERRUPT SEQUENCE FOR AN 8086 BASED SYSTEM

Fig:- Interrupt sequence and registers

involved

PROGRAMMING THE 8259A

Involves writing necessary control words into control
registers.
Two types of control words.
Initialization Command Word(ICW)
-Needed for starting the operation
- Sequences of 4 bytes
Operational Control Word(OCW)
-Words which command 8259 to operate in various
interrupt modes. They are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode

Values of A0 for different ICWs

Initialization Command Word(ICW)

ICW1

ICW2

ICW3 Master
and slave

ICW4

Values of A0 for different OCWs

A0
OCW
0

OCW
2
OCW
3

1
OCW
OCW1 0
1
To mask any of the interrupt
request IR0-IR7.
OCW2
Used to assign priorities to interrupt request.
There is a default priority assigned on initialization.
This can be changed based on the bit patterns of
OCW2.
Priority Options
Fully Nested
Automatic rotation
Specific rotation

Fully Nested
This mode is entered after initialization until another mode is
programmed.
Interrupt requests are ordered in priority from 0(highest) to
7(lowest).
If IR3 and IR4 requests occurs simultaneously, IR3 gets priority.
IR3 can be interrupted by a request on IR2, if the interrupt flag
has been enabled by software.
Automatic Rotation Mode
Used when a just and equitable distribution of service is
needed for devices which is considered to have equal priorities.
Once the interrupt for a device is serviced, it goes to
lowest priority status.
Specific Rotation Mode
Similar to previous mode (Automatic rotation).

OCW3
Can be read to get the status of ISR and IRR.
It is also used to enable some high level features of the chip.

Operational Control
Word(OCW) OCW1

OCW2

OCW3