CHAPTER 8

Memory Banks
8086 has a 16-bit memory bus

which means that data transfer can occur at

a maximum rate of 16 bits (one word) per bus
cycle.
But byte transfer and word transfer must be

possible
For a word transfer, two byte locations must be

accessed

Figure 7.11 | 16-bit memory realized

using two 8-bit memory chips

Upper and lower banks

memory is organized as two banks A 16-bit word

is obtained as the concatenation of two bytes in

two memory banks .

One, the upper bank or high bank (odd memory

bank )with the data corresponding to the upper

byte D8D15.

the other, the lower bank or low bank (even

memory bank) which has the data lines D0D7.

Figure 7.12 | Memory banks of 8086

Memory bank access

For accessing a byte If the address is odd ,the active low BHE

signal will be activated

If the address is even ,the A0 line of the
address is low
For word access , both the banks need to be
activated

Table 7.1 | Status of Control Signals for

Memory Bank Access

Figure 7.13 | Memory banks with the respective

bank enables signals, along with the decoder

Odd Addresses Word

For accessing a word whose address is odd, two

machine cycles are expended.

To avoid this, the EVEN directive can be used to align

all memory accesses at even addresses.

Why Memory Banks?

If both banks are enabled on a byte write operation ,

unwanted data on the data lines will get written onto

the enabled location in the other bank,
which is not admissible.
Thus, when a byte alone is to be written into

memory, it is
important to ensure that only one of the
memory banks is enabled.

Figure 7.14 | Using separate write

strobes

I/O Address Decoding

Only I/O mapped I/O i.e peripheral I/O will be

discussed.
Even though our processor has 20 bits for
address, I/O uses only 16 bits.
Thus I/O port addresses can range from 0000 to
FFFFH and the total I/O space is only 64 K i.e.,
we can use 65,536 different I/O addresses.
However, since the instructions for input (IN)
and output (OUT) are separate, we can have 64
K input ports and 64 K output ports.

Figure 7.16 | Schemes of port

addressing

Output Ports
Output ports use the instruction OUT for

writing into it.

Data from the processor is sent to an output
port during the I/O write cycle.
This data will be available on the data bus
only until the end of a machine cycle.
For the output port to be able to use this data,
it must be latched.
Thus, a latch is mandatory for an output port
set up.

Requirements of an Output Port

To identify/select the specific device, an

address decoder should give a select pulse.

To write into the output device, the IOWR
signal must be active (low).
When both the above two conditions are true,
the data on the data bus is latched.
All the above activities occur during an I/O
write cycle.

Figure 7.17 | Basic output port setup

Figure 7.18 | Output port with 8 LEDs

interfaced to it

Input Ports
Input ports use the IN instruction to receive

data into the processor in the accumulator of

the processor (AL or AX).
An input port requires a tri-state buffer along
with it to ensure that it is isolated from the
bus when it is not selected.

Requirements of an Input Port

To identify/select the specific device, an

address decoder should give a select pulse.

To read from the input device, the IORD signal
must be active (low).
When the above two conditions are true, the
corresponding tri-state buffer gets enabled
and data is transferred to the processor.

Figure 7.19 | Basic input

port

Figure 7.21 | Two sets of switches acting

as two 8-bit input ports

Decoding 16-Bit I/O Addresses

Address lines A0 to A15 should be used by

the address decoder to generate the device

select pulse.

Ports with 16-Bit Data

Bus
However, 16-bit data bus is also possible for I/O
ports.
What becomes different then?
The answer is that, the situation is similar to
the case of memory banks.
Recollect the concept of memory banks.
If each of the 16-bit ports needed to be
accessed as two 8-bit ports as well, we have to
have 8-bit I/O banks.
So we can have I/O banks too, with 8 bits in the
upper bank and 8 bits in the lower bank.

Figure 7.22 | I/O banks

Example 7.7
Design a system with 8 LEDs connected to the

lower 8 bits of the data bus of the 8086 data

bus.
The LEDs must switch ON and OFF with a
delay of 1 second between each switching
action.

Figure 7.18 | Output port with 8 LEDs

interfaced to it

Example 7.7 -solution

Example 7.8
Find the addresses of the two input devices

shown in Figure 7.21 and write a program to

read data from each of these ports and move
it to some other registers.

Figure 7.21 | Two sets of switches acting

as two 8-bit input ports

Example 7.8 -solution

i) Two sets of 8 switches S0 to S7 are connected to the

data bus through two tri-state buffers and this setup

functions as two input ports.

ii) The address of the ports are 8-bit, as only address

lines A0 to A7 have been considered for decoding. Th e

address of the first port is 7EH and that of the second
is 3EH.

iii) The address on the address bus decides which of

the input ports get selected. The tri-state buffer

ensures that the port which is not selected, is isolated
from the bus.

Example 7.8 solution

contd
iv) The program for inputting data from each
of these ports is
STRT: IN AL, 3EH
MOV BL, AL
IN AL, 7EH
MOV DL, AL
Thus, after reading both ports, the switch
settings are available in BL and CL. This data
can be used for processing and/or display.