INTERFACING WITH

DSP BLOCKS
)

INTRODUCTION

A digital signal processor (DSP) is a specialized

microprocessor , with its architecture optimized for the
operational

needs

of

digital

signal

processing.For

performing computations DSP processor needs to be

interfaced with various components such as ADC, DAC,
etc.

These modules need to be interfaced with the DSP block to

work as a single entity.

A general DSP block consist of :

A multiplier
An

adder/Subtractor/Accumulator block.

A FLASH

memory.

A SDRAM
DIP

Switches

BLOCK DIAGRAM OF TMS320C6713 DSK

KEY FEATURES OF TMS320C6713 DSP

PROCESSOR

A Texas Instruments TMS320C6713 DSP operates at

225 MHz .

It has 16 Mbytes of synchronous DRAM and 512

Kbytes of non-volatile Flash memory .

4 user accessible LEDs and DIP switches

Software board configuration through registers
implemented in CPLD

Standard expansion connectors for daughter card use

JTAG emulation through on-board JTAG emulator

with USB host interface or external emulator

Single voltage power supply (+5V)

Functional Overview of the

TMS320C6713 DSK
The

DSP on the 6713 DSK interfaces to on-board

peripherals through a 32-bit wide EMIF (External

Memory Interface).
The

SDRAM, Flash and CPLD are all connected to the

bus.
EMIF

signals are also connected daughter card

expansion connectors

DSP TMS320C6713 DSK

COMPONENTS
CPLD(Programmable Logic):
It is used to implement functionality specific to DSK.
It acts as a "glue" logic that ties the board components
together.
The CPLD implements simple random logic functions
that eliminate the need for additional discrete devices.
It acts as a main controller which controls all the
component of DSP and provides necessary signalling to
them.

AIC23 codec
Codec samples analog signal on the microphone or line
input and converts them into digital data so it can be
processed by DSP.
The codec communicates using two serial channels,
one to control the codecs internal configuration
registers and one to send and receive digital audio
samples.
The codec has a 12MHz system clock.

FLASH MEMORY

Flash memory is an electronic (solid-state) non-volatile

computer storage medium that can be electrically
erased and reprogrammed

Flash can be erased in large blocks commonly referred

to as sectors or pages. Once a block has been erased
each word can be programmed once through a special
command sequence.

Memory Map, C6713

DSK

DIP SWITCHES

The DSK includes 4 software accessible LEDs (D7D10) and DIP switches (SW1).

It provide the user a simple form of input/output. Both

are accessed through the CPLD USER_REG register.

CODEC INTERFACING WITH

DSP

There are certain I/O devices which handle transfer of

one bit at a time. Such devices are referred to as serial
I/O devices or peripherals.

Communication

with

serial

peripherals

can

be

synchronous, with processor clock as reference or it

can be asynchronous.

CODEC, a coder-decoder is an example for synchronous

serial I/O. It has Analog input-output, ADC and DAC.

A coded is a device or computer program for encoding or

decoding a digital data stream or signal.

The signals in SSI generated by the DSP are:

DX: Data Transmit to CODEC.

DR: Data Receive from CODEC.

CLKX: Transmit data with this clock reference.

 CLKR:

Receive data with this clock reference.

FSX:

Frame sync signal for transmit.

FSR:

Frame sync signal for receive, First bit, during

transmission or reception, is in sync with these signals.

RRDY: indicator

for receiving all bits of data.

XRDY: indicator

for transmitting all bits of data.

 On

the CODEC side, signals are:

FS*:

Frame sync signal.

DIN:

Data Receive from DSP.

DOUT:

Data Transmit to DSP.

SCLK:

Tx / Rx data with this clock reference.

SSI between DSP and CODEC

The receiving or transmit activity is initiated at the

rising edge of clock, CLKR/ CLKX. Reception /
Transfer starts after FSR / FSX remains high for one
clock cycle.

RRDY

/ XRDY is initially high, goes LOW to HIGH

after the completion of data transfer.

Each

transfer of bit requires one clock cycle.

Receive Timing for SSI

Transmit Timing for SSI

CODEC PCM3002

Block diagram for CODEC

PCM3002

Analog front end samples signal at 64X over sampling

rate.

ADC is based on Delta-sigma modulator to convert

analog signal to digital form.

Decimation filter reduces the sampling rate and thus

processing does not need high speed devices.

DAC is Delta-sigma modulator, converts digital signal

to analog signal.

LPF smoothens the analog reconstructed signal by

removing high frequency components.

The Serial Interface monitors serial data transfer. It

accepts built-in ADC output and converts to serial data
and transmits the same on DOUT. It also accepts serial

data on DIN & gives the same to DAC.

The serial interface works in synchronization with
BCLKIN & LRCIN.

The Mode Control initializes the serial data transfer. It

sets all the desired modes, the number of bits and the
mode Control Signals, MD, MC and ML. MD carries
Mode Word.
MC is the mode Clock Signal, MD to be loaded is sent
with reference to this clock, ML is the mode Load
Signal. It defines start and end of latching bits into
CODEC device.

Specification of CODEC PCM 3002

PCM3002 CODEC handles data size of 16 / 20 bits.
It has 64x over-sampling, delta sigma ADC & DAC.
It has two channels, called left and right. The CODEC
is programmable for digital de-emphasis, digital
attenuation, soft mute, digital loop back, power-down
mode.
System clock, SYSCLK of CODEC can be 256fs,
384fs or 512fs. Internal clock is always 256fs for
converters, digital filters.

DIN, DOUT are the single line data lines to carry the
data into the CODEC and from CODEC.
LRCIN is frame sync signal for Left and Right
Channels.

THANK YOU