Ones Counter

This example will help you

understand the verification flow

Ones Counter is a Counter which counts the number of one's

coming in serial stream.
The Minimum value of the count is "0" and count starts by
incriminating one till "15".
After "15" the counter rolls back to "0".
Reset is also provided to reset the counter value to "0". Reset
signal is active negedge.
Input is 1 bit port for which the serial stream enters. Out bit is 4
bit port from where the count values can be taken. Reset and
clock pins also provided.

RTL

moduledff(clk,reset,din,dout);
inputclk,reset,din;
outputdout;
logicdout;
always@(posedgeclk,negedgereset)
if(!reset)
dout<=0;
else
dout<=din;
endmodule
moduleones_counter(clk,reset,data,count);
inputclk,reset,data;
output[0:3]count;
dff
dff
dff
dff

d1(clk,reset,data,count[0]);
d2(count[0],reset,~count[1],count[1]);
d3(count[1],reset,~count[2],count[2]);
d4(count[2],reset,~count[3],count[3]);

endmodule

Test Plan :

This is a simple testplan. Features to be verified are

1) Count should increment from "0" to "15".( Coverage item)
2) Count should roolover to "0" after "15".(Coverage
transition)
3) Reset should make the output count to "0", when the count
values is non "0". ( Assertion coverage)

Block Diagram

Verification environment
hierarchy

TOP
|-- Clock generator
|-- Dut Instance
|-- Interface
|-- Assertion block instance ( assertion coverage)
|-- Testcase instance
|-- Environment
|-- Driver
| |-- Stimulus
| |-- Covergroup
|-- Monitor
|-- Scoreboard

Testbench Components

Stimulus
Stimulus is a single bit value.
classstimulus;
randbitvalue;
constraintdistribution{valuedist{0:=1,1:=
1};}
endclass

Driver
This driver consists of reset and drive
method.
Reset method resets the DUT and drive
method generates the stimulus and sends it
to DUT.
Driver also calculates the expected DUT
output and stores in scoreboard.
Coverage is also sampled in this
component.
Feature 1 and 2 which are mentioned in
Testplan are covered in this cover group.

classdriver;
stimulus sti;
Scoreboard sb;
covergroupcov;
Feature_1:coverpointsb.store;
Feature_2:coverpointsb.store{binstrans=(15=>0);}
endgroup
virtualintf_cnt intf;
functionnew(virtualintf_cnt intf,scoreboard sb);
this.intf=intf;
this.sb=sb;
cov=new();
endfunction
taskreset();// Reset method
intf.data=0;
@(negedgeintf.clk);
intf.reset=1;
@(negedgeintf.clk);
intf.reset=0;
@(negedgeintf.clk);
intf.reset=1;
endtask
taskdrive(inputintegeriteration);
repeat(iteration)
begin
sti=new();
@(negedgeintf.clk);
if(sti.randomize())// Generate stimulus
intf.data=sti.value;// Drive to DUT

sb.store=sb.store+sti.value;// Cal exp value and store in Scoreboard

if(sti.value)

cov.sample();
end
endtask

Monitor

The monitor collects the DUT output and then gets the expected value from the
score board and compares them.
classmonitor;
scoreboard sb;
virtualintf_cnt intf;

functionnew(virtualintf_cnt intf,scoreboard sb);

this.intf=intf;
this.sb=sb;
endfunction
taskcheck();
forever
@(negedgeintf.clk)
if(sb.store!=intf.count)// Get expected value from scoreboard and compare
with DUT output
$display(" * ERROR * DUT count is %b :: SB count is %b ",intf.count,sb.store);
else
$display(" DUT count is %b :: SB count is %b ",intf.count,sb.store);
endtask
endclassompares them.

Assertion Coverage

This block contains the assertion coverage

related to 3 rd feature mentioned in
testplan.

moduleassertion_cov(intf_cnt intf);
F3:coverproperty(@(posedgeintf.clk)
(intf.count!=0)|->intf.reset==0);
endmodule

Scoreboard

This scoreboard is a simple one which

stores one expected value.
classscoreboard;
bit[0:3]store;
endclass

Environment

Environment contains instances of driver, monitor and scoreboard.

classenvironment;
driver drvr;
scoreboard sb;
monitor mntr;

virtualintf_cnt intf;
functionnew(virtualintf_cnt intf);
this.intf=intf;
sb=new();
drvr=new(intf,sb);
mntr=new(intf,sb);

fork
mntr.check();
join_none
endfunction
endclass

Interface

The interface is declared and the test bench and

DUT instances are taken. Testbench and DUT are
connected using interfaces. Clock is also
generated and connects it to DUT and testbench.

interfaceintf_cnt(inputclk);
wireclk;
wirereset;
wiredata;
wire[0:3]count;
endinterface

Top

moduletop();
regclk=0;
initial// clock generator
forever#5clk=~clk;
// DUT/assertion monitor/testcase instances
intf_cnt intf(clk);
ones_counterDUT(clk,intf.reset,intf.data,intf.count);
testcase test(intf);
assertion_cov acov(intf);
endmodule

Tests

This is a simple test case. It does reset and then

send 10 input values.

programtestcase(intf_cnt intf);
environment env=new(intf);
initial
begin
env.drvr.reset();
env.drvr.drive(10);
end
endprogram

Coverage Report

(S)Total Coverage Summary

SCOREASSERTGROUP
9.380.0018.75
(S)Cover group report
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALW
EIGHT
Feature_11610637.501001
Feature_21100.001001
(S)Assertion coverage report:
COVERPROPERTIESCATEGORYSEVERITYATTEMPTSMATCHESI
NCOMPLETE
Feature_3001300

This coverage report will be different if you

simulate in your tool.
To improve the coverage, than the 1st
testcase , I wrote 2nd testcase with more
input values and also logic related to 3
feature in the testplan.

Tests

programtestcase(intf_cnt intf);
environment env=new(intf);
initial
begin
env.drvr.reset();
env.drvr.drive(100);
env.drvr.reset();
env.drvr.drive(100);
end
endprogram

Simulation Report

Simulation Log Report:

DUTcount is 0xxx::SBcount is0000
DUTcount is 0xxx::SBcount is0000
DUTcount is0000::SBcount is0000
DUTcount is0000::SBcount is0000
*ERROR*DUTcount is1111::SBcount
*ERROR*DUTcount is0111::SBcount
*ERROR*DUTcount is0111::SBcount
*ERROR*DUTcount is0111::SBcount
*ERROR*DUTcount is1011::SBcount
*ERROR*DUTcount is1011::SBcount
DUTcount is0011::SBcount is0011
DUTcount is0011::SBcount is0011
*ERROR*DUTcount is1101::SBcount

is0001
is0001
is0001
is0001
is0010
is0011
is0100

Phases of Verification

Verification Plan:
Test plan includes, introduction,
assumptions, list of test cases, list of
features to be tested, approach,
deliverables, resources, risks and
scheduling, entry and exit criteria.
Test plan helps verification engineer to
understand how the verification should be
done. A test plan could come in many
forms, such as a spreadsheet, a document
or a simple text file.

Building Testbench:

In this phase, the verification environment is

developed.
Each verification component can be
developed one by one or if more than one
engineer is working it can be developed
parallel.
Writing the coverage module can be done at
any time.
It is preffered to write down the coverage
module first as it gives some idea of the
verification progress.

Writing Tests:

After the TestBench is built and integrated to DUT, it's

time for validating the DUT.
Initially in CDV, the test are ran randomly till some 70
% of coverage is reached or no improvement in the
coverage for 1 day simulation.
By analyzing the coverage reports, new tests are
written to cover the holes.
In these tests, randomization is directed to cover the
holes. Then finally, the hard to reach scenarios, called
as corner cases have to be written in directed
verification fashion.
Of course, debugging is done in parallel and DUT fixes
are done.

Integrating code coverage

Once you have achieved certain level of

functional coverage, integrate the code
coverage. For doing code coverage, the
code coverage tools have option to switch it
on. And then do the simulation, the tool will
provide the report.

Analyze coverage:

Finally analyze both functional coverage

and code coverage reports and take
necessary steps to achieve coverage goals.
Run simulation again with a different seed,
all the while collecting functional coverage
information.

Thank You!