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TRANSMITTER
Research Proposal
Introduction
During all kind of military operations, fast,
efficient and secure communication plays a vital
role to achieve strategic goals.
The goal of this study is to purpose design of
secure digital transmitter using some efficient
and reliable communication technique to achieve
better level of communication security for all kind
of military communications either wired or
wireless.
Design and implementation details of a digital
transmitter will be proposed that will be capable
to transmit data in secure way so that nobody will
be able to intercept and misuse data or observe
its patterns.
Secure
Digital
Transmit
ter
Secure
Digital
Receive
r
Source
Source
Encode
r
Chanel
Encode
r
Modula
tor
Implementation
Using Integrated Circuits:
ICs are very costly.
Implementation
Using Hardware Descriptive Language:
HDLs are standard text-based expressions of
the spatial and temporal structure and
behavior of electronic circuits.
HDLs are used to write the specification of a
digital system. A program is designed using
standard expressions to implement the
characteristics of the underlying system.
Implementation
Using Hardware Descriptive Language:
It is very easy to create these circuits
physically using FPGA (Field Programmable
gate array),
Advantages
Cost effective,
Less complex
Easy to implement
Ease of Testing
Purposed Design
DATA
TRANSFER
VERILOG HDL
Problem Statement
This study is an effort to design a secure
digital communication transmitter, aims to
provide a secure and reliable communication
mechanism using some efficient and reliable
data communication security technique
Significance of Study
Ease of Modification in design in the future.
New dimensions of research can be explored on the basis
of proposed design.
Design in Verilog HDL is Cost and Time Effective.
Ease of Testing is the major benefit of this approach.
Limitation of Study
This study is only limited to the design of a secure digital
transmitter that may be a part of any digital communication
system to transmit the digital signals for any receiver that is
operating on the same mechanism as transmitter it is
because of cost, time and technical facilities availability
constraints that medium and receivers are not considered in
this very project.
The underlying project will be implemented in verilog HDL
and a simulation of the proposed system will be the final
deliverable. It will not be implemented physically because of
technical deficiencies, but that deliverable will be easy to
implement with the help of FPGAs.
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