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Analysis 1
Chapter 5: Operational
Amplifier
Sharifah Azma bt Syed Mustaffa
Operational Amplifier
5.2
Operational Amplifiers
5.3
Ideal Op Amp
5.4
Inverting Amplifier
5.5
Non-Inverting Amplifier
5.6
Summing Amplifier
by KCL,
io = i 1 + i 2 + i + + i -
Ri = input resistance
Ro = output resistance
v1 = voltage between inverting terminal and
ground
v2 = voltage between non-inverting terminal and
ground
Differential input voltage, vd = v2 v1
Output voltage, vo = Avd = A(v2 v1)
where A is the open loop voltage gain
Typical range
Ideal values
Open-loop gain, A
105 to 108
Input resistance, Ri
105 to 1013
Output resistance,
Ro
10 to 100
5 to 24 V
Practical Limitation
KCL at node 1:
KCL at node O:
Circuit Analysis 1 Sem 1 11/12
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And thus,
11
12
13
14
15
16
i1 i2 0
1.
2.
vd v2 v1 0
v2 v1
17
18
19
Rf
vo
Ri
vi
20
i1 i2
vi v1 v1 vo
R1
Rf
And yield to
thus,
v1 v2 0
vi vo
R1 R f
Rf
vo vi
R1
Circuit Analysis 1 Sem 1 11/12
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22
23
Rf
vo 1
vi
R1
24
2.
i1 i2
0 v1 v1 vo
R1
Rf
v1 v2 vi
Voltage gain Av =
vi vi vo
R1
Rf
Constraints:
i1 i2 0
v2 v1
Rf
vo 1 vi
Ri
Rf
vo
1
vi
Ri
25
26
27
Rf
Rf
Rf
vo
v1
v2
v3
R2
R3
R1
28
29
30
R2 (1 R1 / R2 )
R2
R2 R3
vo
v2 v1 vo v2 v1 , if
1
R1 (1 R3 / R4 )
R1
R1 R4
Circuit Analysis 1 Sem 1 11/12
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32
33
34
35
36
37
38
R2
R2
v1
vi
vo
R1
Rf
(1)
vo v2
R4
v1
R3 R4
v1
R3 R4
vo
R4
(2)
39
R3
1
v o
R4
R3
R4
R2
Rf
vo
vi
R2
R1
R1
R2
R1
vo
vi
R2
R1
R2
Rf
vo
vi
1
1
R3
R4
R2
Rf
R2 R4 Rf
R2 R4 R3 Rf R4
Circuit Analysis 1 Sem 1 11/12
Rf
40