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Advanced Microprocessors and

Interfacing

Limitations of the 8-bit Microprocessor

Low speed of execution


Low memory addressing capability
Limited number of general purpose
registers
Less powerful instruction set

8086/8088
16-bit Microprocessor
Launched in 1978
16-bit Data bus
20-bit Address bus

8086/88 Architecture

BIU

EU

8086/88 Architecture
CPU is divided into
1. Bus Interface Unit(BIU)
2. Execution Unit(EU)

BIU
BIU handles all transfers of data and
addresses on the buses for Execution Unit

Sends out addresses


Fetches Instructions
Write data to ports and memory
Reads data from ports and memory

EU
Tells the BIU where to fetch instructions
and data from
Decodes instructions
Execute instructions

The Execution Unit


Includes
Control Circuitry, Instruction Decoder and
ALU
Flag Registers
General-Purpose Registers

Control Circuitry, Instruction Decoder and


ALU

Control Circuitry directs internal operations


A decoder in the ALU translates instructions
fetched from memory into series of actions
16-bit arithmetic logic unit which can

Add
Subtract
AND
OR
XOR
Increment
Decrement

Flag Register
Flip Flop
Indicates some conditions produced by
execution of an instruction
Controls certain operations of EU

Flag Register
Six conditional flags in this group are
Carry Flag
Parity Flag
Auxiliary carry Flag
Zero Flag
Sign Flag
Over Flow
Three Control Flags
Trap Flag
Interrupt Flag
Direction Flag

Flag Register
X

OF DF IF

TF

SF

ZF

AF X

CF- Set by Carry Out of MSB


PF- Set if Result has Even Parity
AF- Set if Carry from bit D3 to D4
ZF- Set if Result =0
SF- MSB of Result
TF- Single step Trap Flag
IF Interrupt Enable Flag
DF String Direction Flag
OF Over Flow Flag

PF

CF

General Purpose Registers


8 General Purpose Registers
AH

AL

AX

BH

BL

BX

CH

CL

CX

DH

DL

DX

General Purpose Registers


AX 16bit Accumulator
CX- used as a default counter in the case
of string and loop instructions
BX- is used as offset storage
DX used as implicit operand and
destination in case of few instructions

Bus Interface Unit


Queue
Segment Registers
Instruction Pointer

The Queue
if the BIU is not busy...the EU is
decoding or executing without the need
of any buses...it can pre-fetch up to 6
instruction bytes
these instructions are stored in a
FIFO register set called a queue
an example of pipelining

Segment Registers
the 220 bytes of addresses are divided in to 4
64KB segments
code segment - CS register stores upper 16 bits of its
starting address
where executable program is stored
stack segment - SS register stores upper 16 bits of its
starting address
stores addresses and data while a subprogram is
executed
data segment - DS register stores upper 16 bits of its
starting address
holds data
extra segment - ES register stores upper 16 bits of its
starting address
holds more data

Advantages of Memory
Segmentation
Allow the memory capacity to be 1Mb
even though the addresses associated
with the individual instructions are only 16
bits wide.
Facilitate the use of separate memory
areas for the program, its data and the
stack.
Permit a program and/or its data to be put
into different areas of memory each time
the program is executed.
Multitasking becomes easy.

Instruction Pointer(IP)
contains the 16-bit address of the next
code byte in the code segment
this is called an offsetit must be added to
the address contained in the CS register,
which is called the base

example:
CS contains the value 348AH
IP contains the value 4214H
whats the physical address of the next code
byte?
you can represent an address in segment
base:offset form348A:4214

Physical Address Generation

4489FH

38AB4H

CS
IP

3
3

Physical Address

348A0H

Top of Code
Segment

Code Byte

Start of Code
Segment

Addressing Modes
Different ways in which processor can
access data is called addressing modes
Data Addressing Modes
Program memory addressing modes
Stack Memory Addressing modes

Data Addressing Modes

Register Addressing
Immediate Addressing
Direct Addressing
Register Indirect Addressing
Base-plus-Index Addressing
Register Relative Addressing
Base relative-plus-index addressing

Register Addressing
Transfers a byte or word from the
source register or memory location to
destination register or memory location
Eg: MOV CX,DX

Immediate Addressing
Transfers the source immediate byte or
word of data into destination register or
memory location
Eg: MOV AL,20H

Direct Addressing
Moves a byte or word between a memory
location and a register
Does not support memory-to-memory
transfer
Eg: MOV AL,[1234H]

Register Indirect Addressing


Transfers a byte or word between a
register and a memory location addressed
by index or base register
The index and base registers are
BP,BX,DI and SI
Eg: MOV AX,[BX]

Base-plus-Index Addressing
Transfers a byte or word between a
register and a memory location addressed
by a base register(BP or BX) plus an index
register (DI or SI)
Eg: MOV DX, [BX+DI]

Register Relative Addressing


Move a byte or word between a register
and a the memory location addressed by
an index or base register or base register
plus a displacement.
Eg: MOV AX,[BX+1000H]

Base Relative plus Index


Addressing
Transfers a byte or word between a
register and a memory location addressed
by a base and an index register plus a
displacement.
Eg: MOV AX,ARRAY[BX+DI]
MOV AX,[BX+SI+100H]

Program Memory-Addressing
Modes
Used with JMP and CALL instructions,
consists of three different forms
Direct Program Memory Addressing
Relative Program Memory Addressing
Indirect Program Memory Addressing

Direct Program Memory


Addressing
Stores address with the operand
Eg: JMP [10000H]
Intersegment jump is a jump to any
memory location with in the entire memory
system.

Relative Program Addressing


Relative means relative to instruction
pointer
Eg: JMP [2]
Intrasegment jump is a jump anywhere
within the current code segment.

Indirect Program Memory


Addressing
JMP AX
JMP CX

Stack Memory Addressing Modes


Holds data temporarily and stores return
addresses for procedures.
LIFO memory
Data are placed into the stack by PUSH
instruction and removed with a POP
instruction
CALL instruction

Stack Memory Addressing Modes


Stack memory is maintained by two
registers
Stack Pointer(SP)
Stack Segment Register(SS)
PUSH
higher order 8-bits are placed in the
location specified by SP-1
Lower order 8-bits are placed in the
location specified by SP-2
SP is decremented by 2
Eg: PUSH BX

Stack Memory Addressing Modes


POP
Lower order 8-bits are removed from
the location addressed by SP
Higher order 8-bits are removed from
the location addressed by SP+1
SP incremented by 2
Eg: POP CX

Minimum Mode 8086 System

A minimum mode of 8086 configuration


depicts a stand alone system of computer
where no other processor is connected.
This is similar to 8085 block diagram with the
following difference.
The Data transceiver block which helps the
signals traveling a longer distance to get
boosted up. Two control signals data
transmit/ receive are connected to the
direction
input
of
transceiver
(Transmitter/Receiver) and DEN* signal
works as enable for this block.

Read Cycle timing Diagram for


Minimum Mode

In the bus timing diagram, data transmit


/ receive signal goes low (RECEIVE) for
Read operation.
To validate the data, DEN* signal goes
low.
The Address/ Status bus carries A16 to
A19 address lines during BHE* (low) and
for the remaining time carries Status
information.
The Address/Data bus carries A0 to A15
address information during ALE going
high and for the remaining time it carries
data.

The TW is Wait time needed to synchronize


the fast processor with slow memory etc.
The Ready pin is checked to see whether
any peripheral needs more time for data
transmission.

Write Cycle timing Diagram for


Minimum Operation

This is the same as Read cycle Timing


Diagram except that the DT/R* line goes high
indicating it is a Data Transmission operation
for the processor to memory / peripheral. Again
DEN* line goes low to validate data and WR*
line goes low, indicating a Write operation.

Bus Request & Bus Grant Timings


in Minimum Mode System

The HOLD and HLDA timing diagram indicates in


Time Space HOLD (input) occurs first and then the
processor outputs HLDA (Hold Acknowledge).

Maximum Mode 8086 System

In the maximum mode of operation of 8086, wherein


either a numeric coprocessor of the type 8087 or
another processor is interfaced with 8086.
The Memory, Address Bus, Data Buses are shared
resources between the two processors.
The control signals for Maximum mode of operation
are generated by the Bus Controller chip 8788.
The three status outputs S0*, S1*, S2* from the
processor are input to 8788.

The outputs of the bus controller are the


Control Signals, namely DEN, DT/R*,
IORC*, IOWTC*, MWTC*, MRDC*, ALE
etc. These control signals perform the
same task as the minimum mode
operation. However the DEN is an active
HIGH signal which has to be converted to
active LOW by means of an inverter.

Memory Read timing in


Maximum Mode

Here MRDC* signal is


used instead of RD* as
in case of Minimum
Mode S0* to S2* are
active and are used to
generate control signal.

Memory Write Timing in


Maximum Mode

Here the maximum


mode write signals are
shown. Please note that
the T states correspond
to the time during which
DEN* is LOW, WRITE
Control goes LOW,
DT/R* is HIGH and
data output in available
from the processor on
the data bus.

RQ*/ GT* Timings in


Maximum Mode

Request / Grant pin may appear that both signals are active low.
But in reality, Request signal goes low first (input to processor),
and then the processor grants the request by outputting a low on
the same pin.

Read & Write Cycle Timing


Diagram of 8088

In 8088, the timing diagram for both Read and


Write are indicated along with Ready signal
and Wait states. In 8088, there are only 8 data
lines as compared to 16 lines in the case of
8086. The figure shown above is for a minimum
mode operation of 8088.