IC Production Process

The basic process used to fabricate monolithic circuits using

silicon planar technology can be categorize as follows

1.Silicon Wafer Preparation

2.Epitaxial Growth
3.Oxidation
4.Photolithography
5.Diffusion
6.Metallization
7.Circuit Probing
8.Scribing and Separating into Chips
9.Mounting and Packaging
10.Encapsulation

SiliconWafer Preperation:
The starting raw material for the wafer preparation is
MGS(Metallurgical Grade Silicon), from which a poly
crystalline material of small impurity is obtained , know an
as Electronic Grade Silicon (EGS) ,by using Hydrogen
reduction method.
The EGS is converted to purer and defect free single
crystal by Czochralski Technique.
Crystal Growth:
The Czochralski technique for growing crystals was
developed by Czochralski. The apparatus consist of
Crystal puller in Quartz crucible.
The poly crystalline EGS along with required amount of
dopant impurities (P-type or N-type ) & heated to a
temperature that is slightly above the silicon melting point
of 1420oC.
A small single-Crystal rod of silicon called a seed crystal is

The seed crystal is slowly pulled up and down of the melt, it

will pull with it a solidified mass of silicon that will be a
crystallographic continuation of the seed crystal.
Both the seed crystal and the crucible and rotated in
opposite directions during the crystalline pulling process in
order to produce the crystalline silicon ingots of circular cross
section of 10 cm to 30 cm in diameter and can be one to two
meters in length.
The ingots are then cut into slices, called as wafers using
diamond tipped saws about 400m to 600m thickness, and
the surface is polished to give a smooth, highly flat region.
The surface of the wafer is then polished to using chemical
and mechanical polishing (CMP) techniques.

Epitaxial Growth
Epitaxy means growing a single crystal structure upon a
original silicon substrate, such that the new structure is
essentially a molecular extension of the original substrate.
The distinct difference between epitaxial and crystal
growing technique is In epitaxy, a thin film of single crystal
silicon is grown from the vapor phase, where as wafers are
grown from the liquid phase. Epitaxy layers can be closely
controlled for their size and resistivity.
Growth of epitaxial layer makes it possible to control the
doping profile in a device structure.. Most of the integrated
circuit structure is formed in the epitaxy layer, the rest of
the slice acting purely as a supporting plane.
Initially, the slices are heated to about 1200oC and pure
hydrogen and hydrochloric acid vapour mixture is passed
over them to each away any oxide or impurities which may
exist on the surface of the silicon. HCl vapour is then cut-off
and hydrogen gas bubbled through SiCl4..

The epitaxy layer may be doped with P or N-type

impurities by introducing these dopants with the required
concentration into the vapour stream.
Four Silicon sources can be used for growing epitaxial
silicon. These are silicon tetra chloride( SiCl4) , dichloro
silane (Si H2Cl2), trichloro silane (Si HCl3), and Silane( Si
H4).
The usual sources of dopants are hybrids of phosphorous,
boron or arsenic. Generally hydrades of the impurities are
used , biborane (B2H6) is used for P-type doping and
Phosphine (PH3) for N-type.
Doping Levels <= 10^17 atoms/Cm3
Depth : 10-15um into substrate, resistivity 10ohm.

Oxidation:
In oxidation, silicon reacts with oxygen to form silicon dioxide (SiO2).
To speed up this
chemical reaction, it is necessary to carry out the oxidation at high
temperatures (e.g.,
10001200C) and inside ultraclean furnaces. This process is called
Thermal Oxidation because high temperature is used to grw the oxide
Note:
layer.
To avoid the introduction of even small quantities of
contaminants (which could significantly alter the electrical
properties of the silicon), it is necessary to operate in a clean
room . Particle filters are used to ensure that the airflow in
the processing area is free from dust. All personnel must
protect the clean-room environment by wearing special lintfree clothing that covers a person from head to toe.

The layer of silicon dioxide serves two important purposes.

i) SiO2 is an extremely hard protective coating. Hence, it is
used for surface passivation and is unaffected by moisture,
reagents except Hydroflouric acid and other atmospheric
contaminants.
ii) It acts as diffusion mask permitting seletive diffusions
into silicon wafer through the windows etched in the oxide. It
is also used for insulating the metal interconnections from the
silicon.
The oxygen used in the reaction can be introduced either as a high-purity
gas (referred to as a dry oxidation) or as steam (forming a wet
oxidation). In general, wet oxidation has
a faster growth rate, but dry oxidation gives better electrical
characteristics. The thermally
grown oxide layer has excellent electrical insulation properties.
Thickness = .02 to 2 um.
Thickness of the oxide layer is governed by time, temperature and
moisture content.

PHOTO LITHOGRAPHY:

The process of photolithography makes it possible to

produce microscopically small circuit and device
patterns on Si wafers.
Lithography refers to the transfer of an image onto
paper
Photolithography is the transfer of an image using
photographic techniques.
Photolithography transferred designer generated
information (device placement and interconnections) to
an actual IC structure using masks which contain the
geometrical information
The process of photolithography is repeated many times
in manufacture of an IC to build up device structures
and interconnections

The photo lithography involves following steps

1. Photo Resist Coating
A Photo Resist is a photo sensitive emulsion. The silicon
wafer is held firm in the vaccum chuck and a drop of
photoresist is applied at the center of oxide layer. The wafer
is then rotated at a speed of 5000rpm. This spin makes the
photoresist to uniformly spread as a thin coating over the
oxide layer. Hence this process is caller Spin Coating.
2. Prebaking of Photo resist
The silicon wafers coated with photoresist are then bake in an
oven at a temperature of 1000 C . This prebaking is necessary
to harden the photoresist coating.
3. Mask Transfer
Photo mask is aligned over the silicon wafer . The photo
mask indicates the location of the windows in the oxide layer
where the SiO2 layer is to be removed . It is a photographic
plate, in which the windows are represented by opaque area
and other areas are made transparent.
4. Resist Development
The entire setup is then exposed to UV light. Photoresisit
under the transparent region of mask becomes polymerized.
The polymerized portions become tougher and they are

5. Selective Removal or Etching.

After UV exposure , the mask is removed and the wafer is

developed using a suitable chemical like trichloroethylene.
This results in the removal of the photo resist film where
windows are required.
After developing , curing is done to the wafer , this makes
polymerized area resistant to corrosion.
Again baked in a oven at 1500C about 20min.
Then wafer is dipped into an etching solution of diluted
hydroflouric acid which removes the oxide layer that is not
protected by photoresist.
The resultant pattern on SiO2 layer , after the etching, is a
pattern of openings or windows which is same as the pattern
on the photo mask. Through these openings, N or P-type
impurities are diffused in various steps of IC fabrication.

Etching
chemical (wet) etching or dry etching procedures can be used.
Chemical etching is usually referred to as wet etching.
Different chemical solutions can be used to remove different
layers.
For example,
hydrofluoric (HF) acid can be used to etch SiO2,
potassium hydroxide (KOH) for silicon,
phosphoric acid for aluminum.
In wet etching, the chemical usually attacks the exposed
regions that are not protected by the photoresist layer in all
directions (isotropic etching). Depending on the thickness of
the layer to be etched, a certain amount of undercut will occur.
If exact dimension is critical, dry etching can be used. This
method is essentially
a directional bombardment of the exposed surface using a

Diffusion
This is an important process in the fabrication of mono lithic ICs.
Diffusion process allows selected areas to be doped to the
required doping profiles.
Diffusion is a process by which atoms move from a highconcentration region to a low concentration region.
The rate at which dopants diffuse in silicon is a strong function of
temperature. Diffusion of impurities is usually carried out at high
temperatures (10001200C) to obtain the desired doping profile.
When the wafer is cooled to room temperature, the impurities are
essentially frozen in position.
NOTE:
At high temperature , the silicon atoms are highly mobile. The
impurity atoms freely move through the silicon lattice. By process
of substitution , the impurity atoms replace the silicon atoms
going from a higher concentration to that of lower concentration.

These dopants can be effectively masked by thin silicon dioxide

layers.

The diffusion process is performed in furnaces similar to

those used for oxidation. The depth to which the impurities
diffuse depends on both the temperature and the processing
time.
The most common impurities used as dopants are boron,
phosphorus, and arsenic. Boron
is a p-type dopant, while phosphorus and arsenic are n-type
dopants.
Diffusion profile is determined by a number of factors ,
namely ,
solid solubility , diffusion temperature, diffusion time and
surface cleanliness .
Solid Solubility : It is defined as the maximum concentration
of impurity which can be dissolved in the sloid diffusant. The
amount of dopant impurity is decided by the dopant profile
required and solid sollubility of diffusant.

Ion implantation
Ion implantation is another method used to introduce
impurities into the semiconductor crystal.
An ion implanter produces ions of the desired dopant,
accelerates them by an electric field, and allows them to
strike the semiconductor surface.
The ions become embedded in the crystal lattice.
The depth of penetration is related to the energy of the ion
beam, which can be controlled by the accelerating-field
voltage.
The quantity of ions implanted can be controlled by varying
the beam current (flow of ions).

This process has the following advantages:

1. Accurate control over doping to within 5%
Since both voltage and current can be accurately
measured and controlled, ion implantation
results in impurity profiles that are much more
accurate and reproducible than can be obtained
by diffusion
2. Very good reproducibility
3. Performed at low temperature.
4. Precise Resistance Values.

Limitations:
i) Annealing at higher temperature is required for avoiding
the crystal damage.
The ion implantation process can cause damage to the
crystal that leaves many of the implanted ions electrically
inactive. This could be set right by the process of annealing in
which the temperature of the wafer is increased to around
8000C after implantation process allowing the ions into
electrically active locations in crystal lattice.
ii) The Possibility of dopant implanting through various layers
of wafer
Ion implantation normally is used when accurate control of
the doping profile is essential for device operation.

Metallization:

Metallization is the final step in the wafer manufacturing

process.
During the manufacture of integrated circuits, it is necessary
to deposit a thin layer of metal on the silicon to form aluminum
interconnections between various components on the chip.
Metallization is also used to produce bonding pads around the
periphery of the chip.
Metallized areas for the bonding of wire lead from the
package to the chip.
The metal films are formed by various methods such as
chemical vapour
Deposition (CVD) and physical vapour deposition (PVD).

The silicon wafers are placed face down around the bell jar, with the
source of metal in the centre. The vacuum commences. The silicon is
then heated to a temperatures range of 100 to 300oC, which causes the
deposited metal to chemically react with the silicon dioxide and adhere
to the wafer surface.

The thickness of the metal film can be controlled by the

length of the sputtering time, which is normally in the
range of 1 to 2 minutes. The metal interconnects can then
be defined using photolithography and etching steps.
Circuit probing
The performance of each of the integrated circuit
fabricated on the wafer is checked electrically by
placing probes on the bonding pads of the ICs. Faulty
chips are identified and discarded after scribing and
separating the individual chips from wafer.
Scribing and separating into chips
The wafer, in which hundreds of ICs are fabricated, is broken
into individual chips by scribing with a diamond-tipped tool.
Mounting and Packaging
The individual chip cannot be directly handled because it is
very small and brittle. Hence, it is soldered to gold plated
header with which leads have already been connected .The
standard packages available are top-hat (TO) package, flat
package and dual-in-line plastic.