PROJECT GUDIE

G.SHYAM KISHORE
ASSOCIATE PROFESSOR

PRESENTED BY
K.TEJASVI
14271D0607

Carry Select Adder (CSLA) is one of the fastest adders used in

many data-processing processors to perform fast arithmetic functions.
From the structure of the CSLA, it is clear that there is scope for
reducing the area and power consumption in the CSLA.

This work uses a simple and efficient gate-level modification to

significantly reduce the area and power of the CSLA. Based on this
modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA)
architecture have been developed and compared with the regular
SQRT CSLA architecture. The proposed design has reduced area and
power as compared with the regular SQRT CSLA with only a slight
increase in the delay.

An adder is the main component of an arithmetic unit.

A complex digital signal processing (DSP)system involves several adders.

An efficient adder design essentially improves the performance of a

complex DSP system.

A Carry select adder consists of two RCA ripple carry adder and one
multiplexer

 CSLA is composed of two n-bit RCAs, where n is the adder bit-

width.

The logic operation of the n-bit RCA is performed in four stages:

1) half-sum generation (HSG)
2) half-carry generation (HCG)
3) full-sum generation (FSG)
4) full-carry generation (FCG)..
Two n-bit operands are added in the conventional CSLA, then
RCA-1 and RCA-2 generate n-bit sum (s0 and s1) and outputcarry (c0 out and c1 out) corresponding to input-carry (cin = 0 and
cin = 1), respectively

EXISTING SYSTEM ALGORITHM

Ripple Carry Adder

Carry propagation is main concern. to reduce this carry-look ahead and

carry select is used.

Each bit has to wait until the pervious carry ha been calculated.

In CSLA design if no .of full adder are increased then the circuit
complexity also increased.

Number of full adder are increased then power consumption increase.

Number of full adder cells increases the area of the design.

More area overhead system

More power consumption

A simple approach is proposed in this paper to reduce the area and power of
SQRT CSLA architecture.

The reduced number of gates of this work offers the great advantage in the
reduction of area and also the total power.

The basic idea of this work is to use Binary to Excess-1 Converter (BEC)
instead of RCA with CIN=1 in the regular CSLA to achieve lower area and
power consumption.

The main advantage of this BEC logic comes from the lesser number of logic
gates than the n-bit Full Adder (FA) structure.

This work evaluate the performance of the proposed designs in terms of area,
power by Xilinx ISE 9.1 and implemented in FPGA (sparton6).

the RCA calculates n-bit sum and out corresponding to Cin = 0. The
BEC unit receives sum and out from the RCA and generates (n + 1)bit
excess-1 code.

The most significant bit (MSB) of BEC represents Carryout, in which

n least significant bits (LSBs) represent sum out.

PROPOSED SYSTEM ADVANTAGES

Less area overhead system

Less power consumption

High speed architecture

SOFTWARE REQUIREMENTS

Model Sim 6.4c

Xilinx 9.1

REAL TIME APPLICATION

Its mainly used in Digital signal processing

Area efficient system like satellite, mobile phones

This is a simple approach to reduce area and delay of SQRT CSLA

using BEC architecture. It has a great advantage to reduction in the
number of gates.