Unit 3

Unit 3 : TLP AND MULTIPROCESSORS
Symmetric and Distributed Shared Memory Architectures

Cache Coherence Issues
Performance Issues
Synchronization Issues
Models of Memory Consistency
Interconnection Networks
Buses
Crossbar and Multi-stage Interconnection Networks
IFETCE/ME/CSE/B.V.R.Raju/Iyear/Isem/CP7103/MCA/Unit-3/PPt/Ver1.0
Symmetric and Distributed Shared Memory

Architectures
Thread-level Parallelism (TLP)

This is parallelism on a more coarser scale
Server can serve each client in a separate
thread (Web server, database server)
A computer game can do AI, graphics, and
physics in three separate threads
Single-core superscalar processors cannot fully
exploit TLP
Multi-core architectures are the next step in
processor evolution: explicitly exploiting TLP
Simultaneous MultiThreading (SMT)

Permits multiple independent threads to execute
SIMULTANEOUSLY on the SAME core
Weaving together multiple threads on the same
core
Example:
if one thread is waiting for a floating point operation to
complete,
another thread can use the integer units
Simultaneous MultiThreading (SMT)

Without SMT, only a single thread can
run at any given time
SMT Processor:
both threads can run
concurrently
But: Cant simultaneously use the

same functional unit
Cache Coherence Issues
Fish Machines
Dual-core Intel Xeon
processors
Each core is hyperthreaded
Private L1 caches
Shared L2 caches
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Private vs Shared
Caches?
Advantages/disadvantages?
Advantages of private:
They are closer to core, so faster access
Reduces contention
Advantages of shared:
Threads on different cores can share the
same cache data
More cache space available if a single (or a
few) high-performance thread runs on the
system
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The Cache Coherence Problem

Since we have private caches:
How to keep the data consistent across
caches?
Each core should perceive the memory as

a monolithic array, shared by all the cores
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Suppose variable x initially contains 15213
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Core 1 reads x
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Core 2 reads x
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Core 1 writes to x, setting it to 21660
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Core 2 attempts to read x gets a stale copy
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Performance Issues
This is a general problem with
multiprocessors, not limited just to multicore
There exist many solution algorithms,
coherence protocols, etc.
simple solutions:
Invalidation-based protocol with snooping
Protocol
Update Protocol
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Invalidation Protocol with

Snooping
Invalidation:
If a core writes to a data item, all other copies
of this data item in other caches are
invalidated
Snooping:
All cores continuously snoop (monitor) the
bus connecting the cores.
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Invalidation Protocol
Core 2 reads x. Cache misses, and loads the new copy
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Update Protocol
Core 1 writes x=21660:
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Invalidation vs Update Protocols

Multiple writes to the same location
invalidation: only the first time
update: must broadcast each write
Writing to adjacent words in the same

cache block:
invalidation: only invalidate block once
update: must update block on each write
Invalidation generally performs better:

it generates less bus traffic
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Synchronization Issues
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Models of Memory Consistency

Shared Memory is memory for which any
processor in the system can access that memory
space. Accessing memory is costly in terms of time
and as a result, Memory may be physically
distributed among processors. (a small record of
parts of the previously accessed memory). When a
processor needs a certain data, it first checks its
cache for the data. If it does not find the data, the
processor then checks either another processors
cache or the memory for the required data. The
problem answered in the lecture was how a system
handles data coherency of the individual caches
and the shared memory. There are a number of
protocols that have been categorized as either
snoopingIFETCE/ME/CSE/B.V.R.Raju/Iyear/Isem/CP7103/MCA/Unit-3/PPt/Ver1.0
or directory based to deal with this
problem.
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Snooping Protocols are based on monitoring bus

activity and carrying out commands depending on that bus
activity. The are four states that might occur when accessing
memory: Read-Hit, Read-Miss, Write-Hit and Write-Miss. A
Read-Hit occurs when a value to be found in memory is
found in the processors cache. A Read-Miss occurs when a
value to be found in memory is not found in the processors
cache. A Write hit occurs when the location in memory to be
referenced is listed in the cache as a latest copy. A Write-miss
occurs when the location in memory to be referenced is not
listed in the cache or is not listed in the cache as a latest
copy(but rather an older copy).
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Buses
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Inter-Core Bus
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Crossbar and Multi-stage

There are three different types of
interconnection networks used with sharedmemory:
1.Uniform memory access (UMA)
2.Non-uniform memory access (NUMA)
3.Cache-only memory architecture (COMA).
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Unit 3

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Unit 3

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Unit 3 : TLP AND MULTIPROCESSORS

Symmetric and Distributed Shared Memory Architectures

Symmetric and Distributed Shared Memory

Thread-level Parallelism (TLP)

Simultaneous MultiThreading (SMT)

Simultaneous MultiThreading (SMT)

But: Cant simultaneously use the

Cache Coherence Issues

The Cache Coherence Problem

Each core should perceive the memory as

The Cache Coherence Problem

The Cache Coherence Problem

The Cache Coherence Problem

The Cache Coherence Problem

The Cache Coherence Problem

Invalidation Protocol with

Invalidation vs Update Protocols

Writing to adjacent words in the same

Invalidation generally performs better:

Models of Memory Consistency

Snooping Protocols are based on monitoring bus

Crossbar and Multi-stage

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