MOS Current Mirrors

By
Lavina Chandwani

Topics Covered
MOS Device Basics
Current Mirrors and Applications
Non Idealities in Current Mirrors
Design of a Simple Current Mirror
Simulations and Results
Architectures of Current Mirrors

MOS Device Basics

General equation for drain current I D is

given by:
}
ID vs VDS curve:

Fig.1.1 ID vs VDS curve

Regions of Operation
Triode
Region

1. VDS << VGS VT

2. ID Equation:

ID VDS MOS acts like a Resistor.

.Saturation
1. VDS VGS VT
2. Maxima of the curve falls at VDS = VGS VT
3. ID Equation:
nCox VT)2
No Dependence of ID on VDS.

Pinch Off and Channel Length

Modulation Effect
In
saturation region ID is not independent of

VDS.
When a voltage at drain exceeds the overdrive
voltage the channel could not be formed at that
point in the substrate.
The channel is said to be PINCHED OFF at
that point and the length of the channel is now
reduced by L.
The new ID equation becomes:
VT)2 where L = L L.
VT)2(1+ VDS)

Slideshow

Fig.1.2a Channel formation

Fig. 1.2b Flow of charges through channel

Fig. 1.2c Pinch Off

CURRENT SOURCES
How do we produce a Stable Current Source ?
RESISTIVE BIASING

Where
Iout poorly defined
1. Dependence on Supply Voltage
2. Dependence on Vt
3. Dependence on Resistor Value variations.
Fig.1.3 Current
Source with
Resistive Biasing

Solution: Make copies of Accurate

Reference Current Source.

CURRENT MIRRORING
Current Mirror is basically a CCCS.
Properties of CCCS(as ideally expected):
1. Current Gain: As Accurate as possible.
2. Rin : Zero
3. Rout : Infinite
4. Output Voltage Compliance: As high as

possible.

CCCS Model

Fig.1.4 Practical CCCS Model

Applications Of CCCS
Biasing
1. In Differential amplifiers.
2. Importance of CMRR dependence on R OUT

of CCCS.
.Active Load
1. When we take single ended output of

Differential amplifier.

SIMPLE CURRENT MIRROR DESIGN

Drain-Gate Feedback.
1. If I1 > I2 Vx increases.
2. If I1 < I2 Vx decreases.

In MOS if Iref > ID then Vx increases and to make

ID= Iref we have to increase Vb.
Connect point X and B.
Advantage: MOS in Saturation.
Accurate Current.
Fig. 1.5 Illustration of Drain Gate
Feedback

Schematic

Neglecting the NonIdealities

As ID depends only on VGS and VGS of both

Mosfets have been kept the same:

For Current Accuracy we keep both MOS in

Saturation region. (Change in VDS does not

affect ID)

Properties
Current
Gain:

For a gain > 1 well vary Width as we have an

option of multiple fingers which reduces
geometrical mismatch and also Length of the
channel is = L - 2 Ld (doesnt double if double L).
Rin:
= =
Rout:
= =0=
Output Swing:
Vout(max.) = VDD
Vout(min.) = VGS VT To keep MOS in saturation.

NON IDEALITIES
Till now we saw ideally what a current

mirror should be.

In our design we ensured:
1. VGS of both Mosfets is same.
2. Both Mosfets are operated in

Saturation Region.
.Non Ideality
1. VDS mismatch
mismatch
3. VT mismatch
2.

VDS MISMATCH
VDS mismatch happens when VDS1 VDS2
We know ID depends on VDS given by:

VT)2(1+ VDS)
Modified Current Gain :
As VDS1 VDS2 , ID1 ID2
Intuitively we can see that to reduce I D we

can reduce
To reduce we can increase L.
But increasing L will increase Area and
Parasitic Capacitances.

 MISMATCH
= nCoxW/L

mismatch can be reduced by placing the Mosfets of the

current mirror close to each other while fabrication.

This will provide both the Mosfets similar
environment and also geometrical mismatches will
reduce.

VT MISMATCH
As ID is dependent on square of VT it is very

important to reduce this mismatch.

Threshold Voltage Mismatch can occur due to
temperature variations over the die and also
through mismatch in Geometrical parameters
of the two mosfets.
To reduce this we can place the mosfets of the
current mirror close to each other.


To
reduce VT mismatch we can increase the Overdrive

Voltage (deceasing gm) but that will reduce Vout swing

of the current mirror.

; can be applied if gain =1

AVT is mismatch coefficient of the MOS pair in current
mirror.
To reduce VT mismatch we can reduce VT by choosing
a MOS having low Mismatch coefficient and high Area.
But increasing area will increase parasitic
capacitances so we go for low AVT mosfets.
Putting values of VT and VGS VT in equation of ID we
get:
It shows ID due to VT mismatch depends only on L

parameter.

Combining all mismatches

The error in output current due to

mismatch in
1. VDS is called Systematic Error and can be
reduced by some architectures (change in
system design).
2. VT and is called Random Error. These are
process (fabrication) dependent errors.

Simulations and Results

Simulation for the given specifications:
1. VDSAT = 200 mV
2. Current Gain = 1
3. Input Current Iref = 2u
4. Output current Accuracy = 1%
.Varying Accuracy and hand calculating W and

L for the transistors.

.MATLAB code for calculating sizing parameters
of the transistors for a given set of
specifications.

Histogram for ID accuracy 1%

Accuracy

Area

Iout
(Theoritical)

Iout
(Practical
)

5.6286

19.5875

110.2502

0.020

0.01800

0.9

6.2540

21.7639

136.1114

0.018

0.01566

0.8

7.0357

24.4844

172.2649

0.016

0.01459

0.75

7.5048

26.1167

196.0006

0.015

0.01305

0.6

9.3810

32.6460

306.2521

0.012

0.01035

0.5

11.2572

39.1750

441.0008

0.010

0.00898

0.4

14.0715

48.9687

689.0631

0.008

0.00690

0.3

18.7620

65.2917

1225.0029

0.006

0.00519

0.2

0.004

0.00351

0.1

0.002

0.00179

Calculations

Accuracy = 1% , ID = 2uA , Gain = 1 , VDsat =

200mV
3 = 0.02uA and = 0.00667uA ,
nCox = 352.915uA/V2 , AVT = 3.5 mV-uA

Also,
Also,
W = 5.6286 m
L = 19.5875 m

CASCODE CURRENT MIRROR

We use Cascode Architecture to reduce VDS

mismatch of the current mirror and to increase

the output impedance of the circuit.

Fig.1.6 Cascode Current Mirror

VX = VGS1+VGS4 =VGS3+VDS2 ,
VGS1=VDS1
VS3 = VX VGS3
Vo (min) = VS3+VGS3 VT3
= VGS1 + VGS4 VT3
The minimum voltage to
keep M3 in
Saturation decreases output
swing of the circuit.
VDS mismatch between M1 &

Small signal model:

Fig.1.7 Small Signal model o

Cascode current mirror.

Selection of Cascode and Mirroring Mosfets

1. To

increase Rout
gm3ro3 should be high
so we select the
transistor with high
gmro value. (Analog
Friendly)
2. To
keep the VT
mismatch as low as
possible we use the
transistor
with
lowest AVT(mismatch
coefficient) value as
low as possible for
the current mirror
transistors. (Low VT).

Schematic

SOURCE DEGENERATION
Source degeneration eliminates the effect of V T

mismatch.
We see that gmeff < gm
Similarly,

if gmR >>1 for both mosfets then,

Fig.1.8 Source Degenerated CM