THE COMMON-SOURCE AMPLIFIER

FET AC Model
The resistance rgs, is assumed to be
extremely large so that an open circuit
between the gate and source can be
assumed. Also rds, is assumed large
enough to neglect.

JFET Amplifier Operation

A self-biased common-source n-channel JFET amplifier
A bias voltage is produced by the drop across RS.
RG, serves two purposes: It keeps the gate at approximately 0 V
dc (because IGSS is extremely small), and its large value
(usually several megohms) prevents loading of the ac signal
source.

A Graphical Picture

DC Analysis
The first step in analyzing a JFET amplifier is to determine the dc
conditions including ID and VS.
ID determines the Q-point for an amplifier and enables you to
calculate VD, so it is useful to determine its value. It can be found
either graphically or mathematically.

Graphical Approach
JFET universal transfer characteristic(transconductance curve)
illustrates the relationship between the output current and the input
voltage. The endpoints of the transconductance curve are at IDSS and
VGS(off).
A dc graphical solution is done by plotting the load line (for the selfbiased case shown) on the same plot and reading the values of VGS
and ID at the intersection of these plots (Q-point).

Example

Plot the transconductance curve. The end points are at IDSS and
VGS(off).
we can plot two additional points quickly by noting from the universal
curve.

 For this particular JFET, the points are plotted as shown in Fig
below
The load line starts at the origin and goes to a point where
ID=IDSS and VGS=IDSSRS.
Add the load line to the graph and read the ID and VGS values
from the intersection (Q-point).
For the graph shown, ID=2.2 mA and VGS = 2.4 V.

Mathematical Approach

AC Equivalent Circuit
To analyze the signal operation
of the amplifier in develop an ac
equivalent circuit as follows.

Signal Voltage at the Gate

Since the input resistance to a JFET is extremely high, practically all
of the input voltage from the signal source appears at the gate with
very little voltage dropped across the internal source resistance.
Vgs = Vin

Voltage Gain:

Example

Solution:

Use either a graphical approach or a mathematical approach with a

graphing calculator to determine ID.

VGS=IDSSRS
VGS=12mA*910ohm=10.92V

Effect of an AC Load on Voltage Gain

The total ac drain resistance is

The effect of RL is to reduce the unloaded voltage gain

Example

Phase Inversion
The output voltage (at the drain) is 180 out of phase with the input
voltage (at the gate).
The phase inversion can be designated by a negative voltage gain, -Av.

Input Resistance
A high input resistance is produced by the reverse-biased pn junction
in a JFET and by the insulated gate structure in a MOSFET.
The actual input resistance seen by the signal source is the gate-toground resistor, RG, in parallel with the FETs input resistance,
VGS/IGSS.
The reverse leakage current, IGSS, is typically given on the
datasheet for a specific value of VGS so that the input resistance of
the device can be calculated.
Since the term VGS/IGSS is typically much larger than RG, the input
resistance is very close to the value of RG.

Example

D-MOSFET Amplifier Operation

A zero-biased common-source n-channel D-MOSFET with an ac
source capacitively coupled to the gate is shown in Fig.
The gate is at approximately 0 V dc and the source terminal is at
ground, thus making VGS=0 V.

 The signal voltage causes Vgs to swing above and below its
zero value, producing a swing in Id.
The negative swing in Vgs produces the depletion mode, and
Id decreases. The positive swing in Vgs produces the
enhancement mode, and Id increases.
The dc analysis of this amplifier is somewhat easier than for a
JFET because ID=IDSS at VGS=0. Once ID is known, the
analysis involves calculating only VD.
The ac analysis is the same as for the JFET amplifier.

E-MOSFET Amplifier Operation

The gate is biased with a positive voltage such that
VGSVGS(th).
As with the JFET and D-MOSFET, the signal voltage produces a
swing in Vgs above and below its Q-point value, VGSQ.
This, in turn, causes a swing in Id above and below its Q-point value,
IDQ, as illustrated in fig.
Operation is entirely in the enhancement mode.

 The circuit in Fig uses voltage-divider bias to achieve a VGS

above threshold.
The general dc analysis proceeds as follows using the E-MOSFET
characteristic equation to solve for ID.

The voltage gain expression is the same as for the JFET and DMOSFET circuits. The ac input resistance is

Example

THE COMMON-DRAIN AMPLIFIER

 The common-drain (CD) amplifier is comparable to the commoncollector BJT amplifier.

As CC amplifier is called an emitter-follower. Similarly, the
common-drain amplifier is called a source-follower. because the
voltage at the source is approximately the same amplitude as the
input (gate) voltage and is in phase with it.
In CD JFET amplifier the input signal is applied to the gate and the
output is taken from the source, making the drain common to both.
Self-biasing is used in this particular circuit.

Voltage Gain

Input Resistance

Common-Gate Amplifier Operation

The common-gate FET amplifier configuration is comparable to the
common-base BJTamplifier.
Like the CB, the common-gate (CG) amplifier has a low input
resistance.
The gate is connected directly to ground.
The input signal is applied at the source terminal through C1. The
output is coupled through C2 from the drain terminal

Voltage Gain

Input resistance:

THE CLASS D AMPLIFIER

The class D differs fundamentally from the other classes because
its output transistors are switched on and off in response to an
analog input instead of operating linearly over a continuous range
of input values.
In a class D amplifier, the output transistors are operated as
switches instead of operating linearly as in the classes A, B, and
AB.
An advantage in audio applications is that a class D amplifier can
operate at a maximum theoretical efficiency of 100% compared to
class A at 25% and class B/AB at 79%.
In practice, efficiencies over 90% can be achieved with class D.
A basic block diagram of a class D amplifier driving a speaker is
shown in Figure below.

Pulse-Width Modulation (PWM)

Pulse-width modulation is a process in which an input signal is
converted to a series of pulses with widths that vary
proportionally to the amplitude of the input signal.

Notice that the pulse width is wider when the amplitude is

positive and narrower when the amplitude is negative.
The output will be a square wave if the input is zero.
The PWM signal is typically produced using a comparator circuit.

 The input labeled + is called the noninverting input, and the input
labeled is the inverting input. When the voltage on the inverting input
exceeds the voltage on the noninverting input, the comparator
switches to its negative saturated output state.
When the voltage on the noninverting input exceeds the voltage on
the inverting input, the comparator switches to its positive saturated
output state.

The comparator inputs are typically very small voltages (mV range)
and the comparator output is rail-to-rail, which means that the
positive maximum is near the positive dc supply voltage and the
negative maximum is near the negative dc supply voltage.
An output of or 24 V peak-to-peak is not unusual. From this, you can
see that the gain can be quite high.
For example, if the input signal is 10 mVpp, the voltage gain is 24
Vpp/10mVpp 2400.
Since the comparator output amplitude is constant for a specified
range of input voltages, the gain is dependent on the input signal
voltage.
If the input signal is 100 mVpp, the output is still 24 Vpp, and the gain
is 240 instead of 2400.

Frequency Spectra
All nonsinusoidal waveforms are made up of harmonic
frequencies.
The frequency content of a particular waveform is called its
spectrum.
When the triangular waveform modulates the input sine
wave, the resulting spectrum contains the sine wave
frequency, finput, plus the fundamental frequency of the
triangular modulating signal, fm harmonic frequencies above
and below the fundamental frequency.
These harmonic frequencies are due to the fast rise and fall
times of the PWM signal and the flat areas between the
pulses.
A simplified frequency spectrum of a PWM signal is shown
in Figure below.

 The frequency of the triangular waveform must be

significantly higher than the highest input signal frequency so
that the lowest frequency harmonic is well above the range of
input signal frequencies.

The Complementary MOSFET Stage

The MOSFETs are arranged in a common-source complementary
configuration to provide power gain.
Each transistor switches between the on state and the off state and
when one transistor is on, the other one is off, as shown in Figure.
When a transistor is on, there is very little voltage across it and,
therefore, there is very little power dissipated even though it may
have a high current through it.
When a transistor is off, there is no current through it and,
therefore, there is no power dissipated.

The only time power is dissipated in the transistors is during the short
switching time.
Power delivered to a load can be very high because a load will have a voltage
across it nearly equal to the supply voltages and a high current through it.

 In a practical case, each MOSFET would have a few tenths of a

volt across it in the on state. There is also a small internal power
dissipation in the comparator and triangular wave generator. Also,
power is dissipated during the finite switching time, so the ideal
efficiency of 100% can never be reached in practice.

Example

The Analog Switch

E-MOSFETs are generally used for switching applications because
of their threshold characteristic, VGS(th).
When the gate-to-source voltage is less than the threshold value, the
E-MOSFET is off.
When the gate-to-source voltage is greater than the threshold value,
the MOSFET is on.
When VGS(th) is varied between VGS(th) and VGS(on), the MOSFET is
being operated as a switch,

Analog Switch Applications

Analog Multiplexer

MOSFET DIGITAL SWITCHING

CMOS (Complementary MOS)

Inverter

NAND Gate
Q1 and Q4 are in parallel ,Q2
and Q3 are in series.
For Vout = VDD
Q1 and Q4 both or any one of
them should be short (on)
and
Q2 & Q3 both or any one of
them must be open (off).
For Vout = 0
Q1 and Q4 both should be
open(off)
or
Q2 & Q3 should be short (on).

NAND Gate

NOR Gate
Q1 and Q4 are in parallel ,Q2 and
Q3 are in series.
For Vout = VDD
Q1 and Q3 both should be short
(on)
and
Q2 & Q4 them must be open
(off).
For Vout = 0
Q1 and Q3 both or any one of
them should be open (on)
or
Q2 & Q4 should be short (on).