VHDL-AMS Simulation of RF MixedSignal Communication Systems

Q
AWGN Level
Data
Source

System
Counter,
BER math
Delay

Erik C. Normark
MSCAD Lab

Outline
Background and Motivation
Design of Mixed-Signal Systems
VHDL-AMS Basics
Design Tools

Simple BPSK Model

System Design
Simulation Results

/4 DQPSK Model
Basic System Design
Design with Viterbi Encoding

Summary and Conclusions

Design of Mixed Signal Systems

Increasing demand for System-On-Chip
RF, analog, digital circuits all on one chip
Fast time-to-market issues

Less established analog automated design process

Bottom-up design approach common
VHDL-AMS promotes multiple abstraction layers
facilitates mixed design approach
Behavioral model refined until physical transistor-level
implementation reached
Promotes re-use of architectural code

Motivation
Create a mixed-signal, system-level
model of a high-frequency transceiver
in VHDL-AMS
Ability to measure system performance
Through Bit-error-rate (BER) analysis

Compare results of VHDL-AMS

simulations with other available mixedsignal modeling environments.

VHDL-AMS Language Basics

Extension of VHDL standard
Adds support for DAEs and conservative
quantities
Supports description and simulation of analog,
digital, mixed signal, multi-physics devices
Encourages device modeling at various
architecture levels (ideal, non-linear, transistor)

Design Tools
ADVance-MS (ADMS)
Compiler and simulator for VHDL, VHDLAMS, Verilog, Verilog-A, SPICE, C
Supports most of VHDL-AMS standard
No support for file I/O, Procedural, frequencydomain noise

Agilent ADS
Commercial RF design environment for
system-level design modeling and
simulation

BPSK System
Data Source
(Random
Data)

Modulator
(p /4 DQPSK)

Propagation
Channel
(AWGN)

Demodulator
(p /4 DQPSK)

2.4GHZ

Evaluate system performance via comparison

to theoretical BER calculation
Ideal System Architecture

Transmitter
Noisy Channel
Receiver
BER Calculation

How Ideal?
Oscillator:
V==10**(A/20.0)*cos(math_2_pi*f*now + Ph);

PA and LNA:
vo == vi*10**(gain/20.0);

Mixer:
vout==v1 * v2;

BPSK : Transmitter
500 MHz

Uniform
Random
Data

Std_logic to bi-polar
(1 -> +1V,
0 -> -1V)

Power
Amplifier

2.4GHZ

Modulate data by shifting phase of

oscillator between 180o

BPSK Transmitted Spectrum

BPSK : Propagation Channel

AWGN
Anoise
A1 , t 1

Basic channel with variable Additive White Gaussian

Noise Power
Can expand this architecture to include delay spread
Box-Muller transformation of two uniform,
independent random variables

WGN Generator Process

noise_calc : process (noise_s)
variable s1 : positive := seed1;
variable s2 : positive := seed2;
variable x1,x2 : real; -- Uniform random variables
begin
UNIFORM(s1,s2,x1); -- create two uniform variables
UNIFORM(s1,s2,x2);
-- create Gaussian variable using Box-Muller method
noise_s <= SQRT(-2.0*LOG(x1))*COS(2.0*MATH_PI*x2)
after rate;
end process noise_calc;
vo == 10.0**(level/20.0)*noise_s;

AWGN Testing

BPSK : Received Spectrum

BPSK : Receiver
Low
Noise
Amplifier

LPF

A/D

2.4GHZ

Normally Requires coherent detection

Uses original oscillator from transmitter
blocks to bypass this requirement
Design verification only

BER Calculation
AWGN Level

Data
Source

System
Counter,
BER math
Delay

Good estimate of system performance in the

presence of noise
Used Monte Carlo method to measure BER
Sequence of Bernoulli trials
Minimum knowledge of system required

BPSK : BER Calculations

Theoretical BER :

1
Pb erfc
2

Pb : Probability of a bit error (BER)

b : Power level of bit (Eb/No)

BER : Confidence Intervals

P y p y 1
d2
4n
1
1 1

2n
d

N : number of trials
n
y
N

n : number of errors

1
2

t 2 2

dt 1

0.1

1.644

0.05 1.96
0.01 2.58

BPSK : Results

Basic /4 DQPSK System

Data
source

Transmitter

RF
channel

Receiver
Symbol timing
recovery

DQPSK system
wrapper

BER tester
BER wrapper

Ideal System and Architecture

No coherent demodulator required
Less complex receiver implementation
Better spectral characteristics than QPSK, BPSK

Standard for US and Japanese cell phones

/4 DQPSK : Transmitter
1 -> +1V
0 -> -1V
1 GHz

Uniform
Random
Data

Serial to
two-bit
Parallel

Pulse Shaping
3-pole LPF
Fc = 500MHz

Symbol Mapper
(I Q Modulator)
1 -> +1V
0 -> -1V
B

Parallelize Data
Map Symbols
Pulse Shape
Up-convert and amplify

Pulse Shaping
3-pole LPF
Fc = 500MHz

2.4GHZ

90 phase
shift

Power
Amplifier

Signal Constellation
Q

Directly map a pair of

input bits onto relative
phases (/4, 3/4)

Example
Transmit: 00 11 11 01

01

Ak

Bk

0
1
1
0

0
0
1
1

/4
3/4
-3/4
-/4

00
11

11

Symbol Mapping
Sk A cos(c t ( ))
Sk A cos( ) cos(ct ) A sin( ) sin(c t )

I k A cos( )
I k A cos( ) cos( ) A sin( ) sin( )
Similarily :
Qk A sin( )
Qk A sin( ) cos( ) A cos( ) sin( )

Symbol Mapping Code

Uses state machine to implement:
I k I k 1 cos( ) Qk 1 sin( )
Qk Qk 1 cos( ) I k 1 sin( )

Initial state must be on constellation point

Transmitted Constellation

Transmitted Spectrum

/4 DQPSK : Receiver
2.4GHZ

Low
Noise
Amplifier

90 phase
shift

3-pole
LPF Fc =
500MHz
3-pole
LPF Fc =
500MHz

A/D
IQ
Demodulator

A/D

2-bit Parallel
to Serial
Converter

Symbol Timing
Recovery

Four Steps:
Amplify and down-convert
Filter
Demodulate and recover symbol clock
Digitize and Serialize

Data Out

Received Spectrum

Received Constellation: Low Noise

Received Constellation: High Noise

IQ Demodulation
sign(cos( k )) sign(Qk Qk 1 I k I k 1 )
sign(sin( k )) sign(Qk I k 1 I k Qk 1 )
If (cos k 0) then A k 1, else A k 0
If (sin k 0) then Bk 1, else B k 0

IQ Demodulator Code
-- Perform A, B recovery
Ip == Ik'delayed(Tsym);
Qp == Qk'delayed(Tsym);
Atemp == Qk*Qp+Ik*Ip;
Btemp == Ip*Qk-Ik*Qp;

To recover parallel data, pass Atemp

and Btemp through threshold detector
Digitize, Serialize

Symbol Timing Recovery

I
Q

I2+Q2

Narrow BPF
Q = 50

Threshold
Detector

Squaring and adding I, Q channels produces

tone at symboling frequency
High-Q BPF isolates tone
Threshold detector creates std_logic clock at
symbol frequency
transitions in middle of bit period

More complex : feed BPF signal through PLL

more noise-immune

/4 DQPSK : Viterbi Encoder / Decoder

Data source
and encoder

Transmitter

RF
channel

Receiver
Decoder
Symbol timing
recovery

DQPSK system
wrapper

BER tester
BER wrapper

Added a simple rate 3/10 Viterbi encoder

Decreases BER
Increases design size x2
Half clock rate and removal of serial to
parallel conversion

Viterbi Encoder
Output Bit 1
Input Bit

Output Bit 0

Rate 2/3 encoder (K=3)

Operates on 3 input bits and two bits
from cleared register
Produces specific 10 output bits
Less complex Decoder

Viterbi Decoder

Implemented as state machine

Makes decision on correct 3-bit output
after 10 bits received
Less complex but less error tolerant
Large code size

BER with Pulse-Shaping Filters

BER With Viterbi Encoder

Summary of Results
Basic coverage of VHDL-AMS language
BPSK design example
Similar results to theoretical and HP-ADS
Verified noise modeling technique
Small, highly ideal model

/4 DQPSK design
BER closely matches Agilent ADS and theoretical curves
Increased model complexity with encoder / decoder
Verifies that complete system modeling can be easily
performed in VHDL-AMS

Extensions of Research
Increase complexity of model to include
non-linear effects in subsystems
Add delay-spread model to propagation
channel for multi-path simulation
Continue iterative design process

Acknowledgements
Special thanks to:
Dr. Richard Shi and MSCAD Lab
RF group members Pavel Nikitin,
Cherry Wakayama, Lei Yang

Questions?