EE6008

MICROCONTROLLER
BASED SYSTEM DESIGN
BE-EEE 07 SEMESTER
Collected by
C.GOKUL
AP/EEE
Velalar College of Engg & Tech,Erode

Syllabus
EE6008 MICROCONTROLLER BASED SYSTEM
DESIGN

UNIT-1
INTRODUCTION TO PIC
MICROCONTROLLER

UNIT-1 Syllabus
INTRODUCTION TO PIC MICROCONTROLLER

Introduction to PIC Microcontroller

PIC 16C6x and PIC16C7x Architecture
PIC16cxx Pipelining
Program Memory Considerations
Register File Structure
Instruction Set
Addressing Modes
Simple Operations

Introduction to
PIC
Microcontroller

What is PIC?
The term PIC or Peripheral Interface Controller,
has been coined by Microchip Technology Inc.
Low-end range, mid-range and high end range of
controllers.

PIC Architecture: Background

Were used to the Von-Neuman Architecture
Used in: 80X86 (PCs), 8051, 68HC11, etc.)
Only one bus between CPU and memory
RAM and program memory share the same bus and
the same memory, and so must have the same bit
width
Bottleneck: Getting instructions interferes with
accessing RAM
Memory

CPU

(&
Data)

PIC Architecture: Background

PICs use the Harvard Architecture
Used mostly in RISC CPUs (well get there)
Separate program bus and data bus: can be
different widths!
For example, PICs use:
Data memory (RAM): a small number of 8bit
registers
Program memory (ROM): 12bit, 14bit or 16bit
wide (in EPROM, FLASH, or ROM)
Memory

Memory
(Data)

CPU

12
14
16

(Program
)

Von Neumann & Harvard

Architecture

Von Neumann
Architecture:

Fetches instructions and

data from a single memory
space

Limits operating bandwidth

Harvard Architecture:

2006 Microchip Technology Incorporated. All Rights Reserved.

101 ASP

Uses two separate memory

spaces for program
instructions and data
Improved operating
bandwidth
Allows for different bus
widths
Slide

10

CISC
Traditionally, CPUs are CISC
Complex Instruction Set Computer (CISC)
Used in: 80X86, 8051, 68HC11, etc.
Many instructions (usually > 100)
Many, many addressing modes
Usually takes more than 1 internal clock cycle
(T cycle) to execute
Example:
MC68HC05:
0x55

LDAA

1000

1100

01010101

2 bytes, 2 cycles

RISC
PICs and most Harvard chips are RISC
Reduced Instruction Set Computer (RISC)
Used in: SPARC, ALPHA, Atmel AVR, etc.
Few instructions (usually < 50)
Only a few addressing modes
Executes 1 instruction in 1 internal clock cycle
(Tcyc)
Example:
PIC16CXXX:

MOVLW 0x55

1100XX 01010101

1 word, 1 cycle

What is New in PIC?

High performance RISC CPU with 35 no. of
instruction set only
Harvard Architecture
Pipelined Instructions
And a large number of Peripherals In-built

PIC Microcontrollers

PIC =>Peripheral Interface Controller

Microchip Technology
single-chip microcontrollers
8-bit microcontrollers
Assembler and simulator

Low - end PIC Architectures

12-bit wide instructions
functions.
limited program memory

with

basic

I/O

applications
requiring
simple
interface
functions and small program & data memories
12C5XX
16C5X
16C505

Mid range PIC Architectures

low-end architectures + more number of
peripherals + more number of registers + more
data/program memory
16C6X
16C7X
16F87X
Program memory type
C = EPROM
F = Flash
RC = Mask ROM

Popularity of the
PIC microcontrollers
Speed:
Harvard
Architecture,
RISC
architecture, 1 instruction cycle = 4 clock
cycles
Instruction set simplicity: 35 instructions
Power-on-reset and brown-out reset
A watch dog timer (user programmable)
Four optional clock sources
Low power crystal, Mid range crystal, High
range crystal, RC oscillator (low cost)

Popularity of the
PIC microcontrollers
Programmable timers and on-chip ADC
Up to 12 independent interrupt sources
Powerful output pin control (25 mA (max.)
current sourcing capability per pin.)
EPROM/OTP/ROM/Flash memory option
I/O port expansion capability
Free assembler and simulator support from
Microchip at www.microchip.com

CPU Architecture
Harvard Architecture
instruction fetch & operation on data/accessing
of variables simultaneously

PIC Memory Organisation

Program memory address
= 13 bits
Can address up to 8k
Program counter = 13-bit
PIC 16C6X => 2k (11 bits)
PIC16C7X => 4k (12 bits)

program memory map of PIC16C74A

Specifications
Popular PIC microcontrollers
Special purpose register file (similar to SFR
in 8051).

PIC Microcontroller Clock

Can operate upto 20MHz
One instruction cycle (machine cycle)
consists of four clock cycles

Instructions : PC content no change 1

instruction cycle

PIC 16C6x &

PIC16C7x
Architecture

Architecture of PIC16C74A
PC=13 bit
PM=14 - bit word
Program Memory
capacity
= 8k x 14 bit
Each instruction
of PIC 16C74A is
14 - bit long.

Port Structure and Pin Configuration

CPU registers
W, the working register
STATUS Register

C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode

FSR Register
(File Selection Register, address = 04H, 84H)
- 8-bit register - data memory address pointer
- indirect addressing mode.

CPU registers
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register.
- Accessing INDF access is the location pointed to
by FSR in indirect addressing mode.

PCL Register
(Program Counter Low Byte, address = 02H,
82H)
- lower 8-bits of the 13-bit program counter.
- both readable and writable register.

CPU registers
PCLATH Register
(Program Counter Latch, address = 0AH, 8AH)

Program Counter Stack

- An independent 8-level stack
- Organized as 8x13bit registers.

Pipelinin
g

Pipelining of instruction fetch successive

addressing

Introduction of extra cycle for a jump /

goto instruction

Program
Memory
Considerations

Program Memory

The 6x/7x family controllers have either 2k or 4k

address of program memory.
Normally a program memory of 2k addresses
needs only a 11-bit program counter to access
any address (2^11=2048=2k).
A program memory of 4k address needs a 12-bit
program counter.
But this PIC family uses 13-bit program counter
allowing the controllers to an 8k-program
memory without changing the CPU structure.

 Two addresses in the program memory

address space are treated in a special way
by the CPU. The first address H 000 being
a go to mainline instruction the second
special address, H 004 being a go to in
service instruction can be assigned to this
address to make the CPU to jump to the
beginning of the Interrupt Service routine
located elsewhere in the memory space.

 When we deal with tables, if any tables

are created they are assigned to
addresses in the range H005 H0FF.
For most of the applications this space is
sufficient.
The main line program begins after the
tables.

Register
File
Structure

Register File Structure

Register File
Map

Bank - 0 and Bank -1

Some Registers in
both
Changes occur in both

Instructio
n Set of
PIC

Instruction Set

cont

Instruction
Descriptions

ADDLW K
Add

the literal value K to register WREG and

put the result back in the WREG register
(W) + k (W)
K is an 8-bit value: 0-255 (decimal), 00-FF
(hex)
L: literal (actual value)
Affect STATUS bits: C, DC, Z

ADDLW K
Instruction: ADDLW

cont

15H

Before

After

W = 10H

W = 25H

ADDWF f, d
Add

together contents of WREG and a file

register location (SFR @ GPR).
Put the result in the register WREG if d = 0
otherwise it is stored back in register f.
(W) + (f) (d)
0 f 127, d [0, 1]
Affect STATUS bits: C, DC, Z

ADDWF f, d
Instruction: MOVLW
17H
ADDWF 5H, 0
Before

After

W = 0H
5H = 0H

W = 17H
5H = 0H

cont

MOVF f, d
Move the content of f register upon the status of
d
(f) (d)
Affect bit Z of STATUS register

Instruction: MOVF
Before
W = 09AH
FSR = 0H

FSR, 0
After

W = value in FSR register

Z=1

MOVLW

Load k literal into WREG register

k (W)
Dont cares will be assembled as 0s
Not affect bit of STATUS register

Instruction: MOVLW
Before
W = 09AH

After
W = 5AH

5AH

MOVWF f
Move data from WREG register to f register
(W) (f)
Not affect bit of STATUS register

Instruction: MOVWF
Before
PORTB = 00H
W = 09AH

PORTB
After

PORTB = 09AH
W = 09AH

ANDLW k
Logical

AND k literal with the content of WREG

register & the result is placed in the WREG register
(W) AND k (W)
Affect Z bit of STATUS register

Instruction: ANDLW
Before
W = A3H

5FH

After
W = 03H

ANDWF f, d

AND the WREG register with f register

(W) + (f) (d)
Affect Z bit of STATUS register

Instruction: ANDWF
Before
W = 17H
FSR = 0C2H

FSR, 1

After
W = 17H
FSR = 02H

BCF

f, b

Clear bit b in file register

0 (f<b>)
Not affect on STATUS register

Instruction: BCF STATUS, 5

Before

After

STATUS = 0A7H STATUS = 087H

BSF

f, b

Set bit b in f register

1 (f<b>)
Not affect on STATUS register

Instruction: BSF INTCON, 7

Before

After

INTCON = 0BH

INTCON = 08BH

BTFSS f, b

Execute the next instruction if bit b in file register f is

0, otherwise discard executing next instruction
2-cycle instruction
Not affect on STATUS register

Instruction: H BTFSS STATUS, 2

I GOTO LOOP
J

Before
PC = address H

After
PC = Add. J if STATUS<2> = 1,
PC = Add. I if STATUS<2> = 0

BTFSC f, b

Execute the next instruction if bit b in file register f is

1, otherwise discard executing next instruction
2-cycle instruction
Not affect on STATUS register

Instruction: H BTFSC PORTA, 3

I GOTO LOOP
J

Before

After

PC = address H

PC = Add. J if PORTA<3> = 0,
PC = Add. I if PORTA<3> = 1

CALL k

Call subroutine
(PC) + 1 TOS (top of stack)
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction
Not affect on STATUS register

Instruction: SO CALL THEN

Before

After

PC = add. SO

PC = add. THEN;
TOS = add. SO+1

CLRF f
Clear the content of f register
00h (f)
1 Z

Instruction: CLRF PORTA

Before
PORTA = 5AH

After
PORTA = 00H
Z=1

CLRW
Clear the content WREG register
00h (W)
1 Z

Instruction: CLRW
Before
W = 5AH

After
W = 00H
Z=1

COMP f, d
Complement the content of f register
(f) (d)

Instruction: COMP ONE, 0

Before
ONE = 13H
W = 02H

After
ONE = 13H
W = 0ECH

DECF f, d
Decrease f register
(f) 1 (d)

Instruction: DECF CNT, 1

Before
CNT = 01H
Z=0

After
CNT = 00H
Z=1

DECFSZ f, d

Decrease f register and skip the next instruction if the result is 0;

otherwise execute the next instruction
(f) 1 (d), skip if result = 0
2-cycle instruction

Instruction:

HERE DECFSZ CNT, 1

GOTO HERE
CONT
..

Before

After

PC = add. HERE

CNT = CNT - 1
PC = add. CONT if CNT = 0;
PC = add. HERE + 1 if CNT 0

GOTO k

Unconditional branch
k PC<10:0>
(PCLATCH<4:3>) PC<12:11>
2-cycle instruction

Instruction: HERE

GOTO THERE

THERE

Before
PC = add. HERE

After
PC = add. THERE

INCF f, d

Increase the content of f register

(f) + 1 (d)
d is destination

Instruction: INCF SATU, 1

Before
SATU = 0FFH

After
SATU = 00H
Z=1

INCFSZ

f, d

Increase the content of f register and skip the next instruction if the
result is 0; otherwise execute the next instruction
(f) + 1 (d), skip if result = 0
2-cycle instruction

Instruction: HERE INCFSZ CNT, 1

GOTO
loop
CONT
..

Before

After

PC = add. HERE

CNT = CNT + 1
PC = add. CONT if CNT = 0;
else add. HERE + 1

IORLW k
Inclusive OR literal k with the content of WREG
register
(W) OR k (W)
Affect bit Z of STATUS register

Instruction: IORLW
Before
W = 09AH
Z=?

35H
After

W = 0BFH
Z=0

IORWF f, d
Inclusive OR the content of WREG register with f
register
(W) OR (f) (d)
Affect bit Z of STATUS register

Instruction: IORWF
Before
RESULT = 13H
W = 91H

RESULT, 0
After

RESULT = 13H
W = 93H
Z=0

NOP

No operation

Instruction: NOP

RETFIE
Return from interrupt
TOS PC
1 GIE (Global Interrupt Enable)
Not affect bit of STATUS register

Instruction: RETFIE
Before

After
PC = TOS
GIE = 1

RETLW

Return with loading literal k onto WREG

register, k (W)
TOS PC
Not affect on STATUS register

Instruction: RETLW
Before
W = 09AH

088H
After

W = 088H

RETURN
Return from subroutine
POP the TOS and load into the PC
2-cycle instruction

Instruction: RETURN
Before

After
PC = TOS

RLFf, d

Rotate left f through carry

Affect bit C of STATUS register

Instruction: RLF REG, 1

Before

After

REG = 1111 1111 = 0FFH

C=0

REG = 1111 1110 = 0FEH

C=1

RRF f, d

Rotate right f through carry

Affect bit C of STATUS register

Instruction: RRF REG, 1

Before

After

REG = 1111 0111 = 0F7H

C=0

REG = 0111 1011 = 07BH

C=1

SLEEP
00h WDT
0 WDT prescalar
1 TO
0 PD
Affect TO & PD bits of STATUS register

Instruction: SLEEP

SUBLW

Subtract WREG register (2s complement) from literal k

and put the result onto WREG register
k (W) (W)
Affect C, DC & Z bits of STATUS register

Instruction: SUBLW

02H

Before

After

W = 01H
C=?
Z=?

W = 01H
C=1
Z=0

SUBWF f, d

Subtract WREG register (2s complement) from f register

(f) (W) (d)
Affect C, DC & Z bits of STATUS register

Instruction: SUBWF

02H, 0

Before

After

W = 01H
F = 05H
C=?
Z=?

W = 04H
F = 05H
C=1
Z=0

SWAPF f, d
Exchange the upper & lower nibbles of f register
(f<3:0) (d<7:4>), (f<7:4) (d<3:0>)
Not affect STATUS register

Instruction: SWAPF
Before
ON = 0F4H
W = 09AH

ON, 1

After
ON = 04FH
W = 09AH

XORLW k
Exclusive OR (XOR) the content of WREG
register with k literal
(W) XOR k (W)
Store the result in WREG register
Affect bit Z of STATUS register

Instruction: XORLW
Before
W = 0B5H

0AFH
After
W = 01AH

XORWF f, d
Exclusive OR (XOR) the content of WREG
register with f register
(W) XOR (f) (d)
Affect bit Z of STATUS register

Instruction: XORWF
Before
REG = 0AFH
W = 0B5H

REG, 1
After

REG = 01AH
W = 0B5H

PIC16
Addressing
Modes

Addressing Modes
Direct Addressing
-through a 9-bit address (7 bits of direct address of an
instruction with two bits (RP1, RP0) from STATUS register)
Any access to SFR registers is an example of direct
addressing.

Addressing Modes
Indirect Addressing
-derives it from IRP bit of STATUS and FSR registers.
-Addressed location is accessed via INDF register which
in fact holds the address indicated by a FSR.
One general purpose register (GPR) at
address 0Fh contains a value of 20.

By writing a value of 0Fh in FSR register

we will get a register indicator at
address 0Fh, and by reading from INDF
register, we will get a value of 20, which
means that we have read from the first
register its value without accessing it
directly (but via FSR and INDF).

Simple
operation
Programs

UNIT II
INTERRUPTS &
TIMER

UNIT-2 Syllabus
INTERRUPTS AND TIMER

PIC Micro Controller Interrupts

External Interrupts
Interrupt Programming
Loop Time Subroutine
Timers
Timer Programming
Front Panel I/O
Soft Keys
State Machines & Key Switches
Display Of Constant & Variable Strings

PIC TIMERS

PIC Peripherals: Timers

Timer-0, Timer-1 and Timer-2.
Timer-0 & Timer-2 are 8-bit timers.
Timer-1 is a 16-bit timer.

PIC16C74
INTERRUPT
LOGIC

UNIT III
PERIPHERALS
AND
INTERFACING

UNIT-3 Syllabus
PERIPHERALS AND INTERFACING
I2C Bus For Peripherals Chip Access
p-47
Bus Operation
Bus Subroutines
Serial EEPROMAnalog To Digital Converter
UART - Baud Rate Selection
Data Handling Circuit And Initialization
LCD And Keyboard Interfacing
ADC Interfacing
DAC Interfacing
Sensor Interfacing

UNIT IV
INTRODUCTION
TO ARM
PROCESSOR

UNIT-4 Syllabus
INTRODUCTION TO ARM PROCESSOR

ARM Architecture
ARM Programmers Model
ARM Development Tools
Memory Hierarchy
ARM Assembly Language Programming
Simple Examples
Architectural Support For Operating Systems

UNIT V

ARM
ORGANIZATION

UNIT-5 Syllabus
ARM ORGANIZATION

3 - Stage Pipeline ARM Organization

5 - Stage Pipeline ARM Organization
ARM Instruction Execution
ARM Implementation
ARM Instruction Set
ARM Coprocessor Interface
Architectural Support For High Level Languages
Embedded ARM Applications